參數(shù)資料
型號: M37544G2ASP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù): 62/75頁
文件大?。?/td> 649K
代理商: M37544G2ASP
7544 Group (QzROM version)
REJ03B0108-0103
Rev.1.03
Mar 31, 2009
page 65 of 72
APPENDIX
NOTES ON PROGRAMMING
1. Processor Status Register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a re-
set.
In particular, it is essential to initialize the T and D flags because
they have an important effect on calculations. Initialize these flags
at beginning of the program.
<Reason>
After a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
Reset
Initializing of flags
Main program
Fig. 2 Stack memory contents after PHP instruction execution
Fig. 1 Initialization of processor status register
(2) How to reference the processor status register
To reference the contents of the processor status register (PS), ex-
ecute the PHP instruction once then read the contents of (S+1). If
necessary, execute the PLP instruction to return the PS to its origi-
nal status.
(S)
(S)+1
Stored PS
(2) Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC or
SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of
the calculation, or is cleared to “0” if a borrow is generated. To de-
termine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calcula-
tion.
3. JMP instruction
When using the JMP instruction in indirect addressing mode, do
not specify the last address on a page as an indirect address.
4. BRK instruction
(1) Interrupt priority level
When the BRK instruction is executed with the following condi-
tions satisfied, the interrupt execution is started from the address
of interrupt vector which has the highest priority.
Interrupt request bit and interrupt enable bit are set to “1”.
Interrupt disable flag (I) is set to “1” to disable interrupt.
5. Multiplication and Division Instructions
(1) The index X mode (T) and the decimal mode (D) flags do not
affect the MUL and DIV instruction.
(2) The execution of these instructions does not change the con-
tents of the processor status register.
2. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper
decimal notation, set the decimal mode flag (D) to “1” with the
SED instruction. After executing the ADC or SBC instruction, ex-
ecute another instruction before executing the SEC, CLC, or CLD
instruction.
Set D flag to “1”
ADC or SBC instruction
NOP instruction
SEC, CLC, or CLD instruction
Fig. 3 Instructions for decimal calculations
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