參數(shù)資料
型號(hào): M37544G2ASP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù): 13/75頁
文件大?。?/td> 649K
代理商: M37544G2ASP
7544 Group (QzROM version)
REJ03B0108-0103
Rev.1.03
Mar 31, 2009
page 20 of 72
Interrupts
The 7544 Group interrupts are vector interrupts with a fixed prior-
ity scheme, and generated by 12 sources: 5 external, 6 internal,
and 1 software.
The interrupt sources, vector addresses(1) , and interrupt priority
are shown in Table 8.
Each interrupt except the BRK instruction interrupt has the inter-
rupt request bit and the interrupt enable bit. These bits and the
interrupt disable flag (I flag) control the acceptance of interrupt re-
quests. Fig. 17 shows an interrupt control diagram.
An interrupt request is accepted when all of the following condi-
tions are satisfied:
Interrupt disable flag.................................“0”
Interrupt request bit...................................“1”
Interrupt enable bit....................................“1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
Table 8 Interrupt vector addresses and priority
Vector addresses (Note 1)
High-order
Priority
Low-order
Interrupt request generating conditions
Remarks
Interrupt source
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
At reset input
At completion of serial I/O data receive
At completion of serial I/O transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At falling of conjunction of input logical level
for port P0 (at input)
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
Not available
At timer A underflow
Not available
At completion of A/D conversion
At timer 1 underflow
Not available
At BRK instruction execution
1
2
3
4
5
6
7
8
9
10
11
12
13
Reset (Note 2)
Serial I/O receive
Serial I/O transmit
INT0
INT1
Key-on wake-up
CNTR0
CNTR1
Timer X
Reserved area
Timer A
Reserved area
A/D conversion
Timer 1
Reserved area
BRK instruction
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