參數(shù)資料
型號(hào): M37544G2ASP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝: 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁(yè)數(shù): 39/75頁(yè)
文件大?。?/td> 649K
代理商: M37544G2ASP
7544 Group (QzROM version)
REJ03B0108-0103
Rev.1.03
Mar 31, 2009
page 44 of 72
Fig. 49 State transition
Stop mode
Wait mode
WIT
instruction
Oscillation stop detection circuit valid
CPUM4←12
MISRG1¨12
Interrupt
STP
instruction
WIT
instruction
Interrupt
MISRG1←02
CPUM3¨12
CPUM3←02
CPUM76¨102
CPUM76¨002
012
112
(Note 2)
CPUM4¨02
MISRG1¨12
MISRG1¨02
Reset released
State 1
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator stop
State 2
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled
State 3
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enabled
State 4
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation stop
On-chip oscillator enabled
Notes on switch of clock
(1) In operation clock source = f(XIN), the following can be
selected for the CPU clock division ratio.
● f(XIN)/2 (high-speed mode)
● f(XIN)/8 (middle-speed mode)
● f(XIN) (double-speed mode, only at a ceramic/quartz-crystal
oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing XIN oscillation.
(3) In operation clock source = on-chip oscillator, the middle-
speed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 → state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
CPUM76 → 102 (State 2 → state 3)
NOP instruction
CPUM4 → 12 (State 3 → state 4)
Double-speed mode at on-chip oscillator: NOP 3
High-speed mode at on-chip oscillator: NOP 1
Middle-speed mode at on-chip oscillator: NOP 0
Reset state
CPUM76¨102
CPUM76←002
012
112
(Note 2)
State 2’
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled
State 3’
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enabled
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