參數(shù)資料
型號(hào)： M37281MAH-XXXSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁(yè)數(shù)： 81/172頁(yè)
文件大?。?/td> 1319K
代理商： M37281MAH-XXXSP
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Rev.1.01 2003.07.16 page 81 of 170
M37281MAH
–
XXXSP,M37281MFH
–
XXXSP,M37281MKH
–
XXXSP, M37281EKSP
8.11.5 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchro-
nizing signal waveform of interlacing system. The dot line 0 or 1 (re-
fer to Figure 8.11.19) corresponding to the field is displayed alter-
nately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the V
SYNC
control signal (refer to Figure
Fig. 8.11.18 I/O Polarity Control Register
8.11.9) in the microcomputer and then comparing this time with the
time of the previous field. When the time is longer than the compar-
ing time, it is regarded as even field. When the time is shorter, it is
regarded as odd field.
The field determination flag changes at a rising edge of V
SYNC
con-
trol signal in the microcomputer.
The contents of this field can be read out by the field determination
flag (bit 7 of the I/O polarity control register at address 0217
16
). A dot
line is specified by bit 6 of the I/O polarity control register (refer to
Figure 8.11.19).
However, the field determination flag read out from the CPU is fixed
to
“
0
”
at even field or
“
1
”
at odd field, regardless of bit 6.
b7 b6 b5 b4 b3 b2 b1 b0
I/
O
p
o
l
a
r
i
t
y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
C
)
[
A
d
d
r
e
s
s
0
2
1
7
1
6
]
B
N
a
m
e
Functions
A
f
t
e
r
r
e
s
e
t R W
I/
O
P
o
l
a
r
i
t
y
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
0
H
SYNC
input polarity
switch bit (PC0)
i
n
p
u
s
w
i
t
c
h
b
i
t
(
0 : Positive polarity input
1 : Negative polarity input
0
1
0 : Positive polarity input
1 : Negative polarity input
0
2
R, G, B output polarity
switch bit (PC2)
0 : Positive polarity output
1 : Negative polarity output
0
3
0
V
S
Y
N
C
t
P
p
C
o
1
l
a
)
r
i
t
y
R W
R W
R W
R
—
Note:
Refer to Fig. 8.11.19.
0 :
“
”
at even field
“
”
at odd field
1 :
“
”
at even field
“
”
at odd field
4
O
s
U
s
w
i
b
i
U
w
T
t
c
1
h
o
b
u
i
t
p
(
u
P
t
C
p
4
o
)
l
a
r
i
t
y
i
t
0 : Positive polarity output
1 : Negative polarity output
0
5
O
T
t
c
2
h
o
b
u
i
t
p
(
u
P
t
C
p
5
o
)
l
a
r
i
t
y
i
t
0 : Positive polarity output
1 : Negative polarity output
0
6
D
s
t
p
(
l
a
C
y
d
)
o
(
t
S
l
e
i
n
e
e
s
o
e
t
l
e
e
)
c
t
i
o
n
P
6
n
0
7
Field determination
flag(PC7)
0 : Even field
1 : Odd field
1
R W
R W
R W
R
—
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is
“
0
”
.
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