- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359059 > M37281MAH-XXXSP (Renesas Technology Corp.) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | M37281MAH-XXXSP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁(yè)數(shù)： | 26/172頁(yè) |
| 文件大小： | 1319K |
| 代理商： | M37281MAH-XXXSP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)
M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Rev.1.01 2003.07.16 page 26 of 170
8.4 TIMERS
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4,
timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer
latch. The timer block diagram is shown in Figure 8.4.3.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the correspond-
ing timer latch (addresses 00F0
16
to 00F3
16
: timers 1 to 4, addresses
021A
16
and 021B
16
: timers 5 and 6), the value is also set to a timer,
simultaneously.
Down counts “nn
16
– 1, nn
16
– 2......., 01
16
, 00
16
” by the input of the
count source from the right after setting to the timer. The interrupt is
requested by a timer overflow at the next count source input in which
the value of the timer becomes “00
16
.”
Each timers are explained below.
8.4.1 Timer 1
Timer 1 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
f(X
IN
)/4096 or f(X
CIN
)/4096
External clock from the TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F4
16
). Either f(X
IN
) or f(X
CIN
) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
8.4.2 Timer 2
Timer 2 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
Timer 1 overflow signal
External clock from the TIM2 pin
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F4
16
). Either f(X
IN
) or f(X
CIN
) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8-
bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
8.4.3 Timer 3
Timer 3 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
f(X
CIN
)
External clock from the TIM3 pin
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F5
16
) and bit 6 at address 00C7
16
. Either f(X
IN
)
or f(X
CIN
) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
8.4.4 Timer 4
Timer 4 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
f(X
IN
)/2 or f(X
CIN
)/2
f(X
CIN
)
Timer 3 overflow signal
The count source of timer 4 is selected by setting bits 1 and 4 of
timer mode register 2 (address 00F5
16
). Either f(X
IN
) or f(X
CIN
) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8-
bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
8.4.5 Timer 5
Timer 5 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
Timer 2 overflow signal
Timer 4 overflow signal
The count source of timer 5 is selected by setting bit 6 of timer mode
register 1 (address 00F4
16
) and bit 7 of timer mode register 2 (ad-
dress 00F5
16
). When overflow of timer 2 or 4 is a count source for
timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(X
IN
) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
8.4.6 Timer 6
Timer 6 can select one of the following count sources:
f(X
IN
)/16 or f(X
CIN
)/16
Timer 5 overflow signal
The count source of timer 6 is selected by setting bit 7 of timer mode
register 1 (address 00F4
16
). Either f(X
IN
) or f(X
CIN
) is selected by bit
7 of the CPU mode register. When timer 5 overflow signal is a count
source for timer 6, timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF
16
” is
automatically set in timer 3; “07
16
” in timer 4. The f(X
IN
)
/16 is se-
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF
16
” is automatically set in timer 3; “07
16
” in timer 4.
However, the f(X
IN
)
/16 is not selected as the timer 3 count source.
So set both bit 0 of timer mode register 2 (address 00F5
16
) and bit 6
at address 00C7
16
to “0” before execution of the STP instruction
(f(X
IN
)
/16 is selected as the timer 3 count source). The internal
STP state is released by timer 4 overflow in this state and the inter-
nal clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
: When bit 7 of the CPU mode register (CM7) is “1,” f(X
IN
) be-
comes f(X
CIN
).
The timer-related registers is shown in Figures 8.4.1 and 8.4.2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37281MFH-XXXSP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37281MKH-XXXSP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37534E4GP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37534E4FP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37544 | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37281MFH-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37281MKH-XXXSP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M372899234 | 制造商:ITW Switches 功能描述:IN-RUSH |
| M372F3200DJ3-C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V |
| M372F3280DJ3-C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。