參數(shù)資料
型號： M37281MAH-XXXSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 33/172頁
文件大?。?/td> 1319K
代理商： M37281MAH-XXXSP
Rev.1.01 2003.07.16 page 33 of 170
M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at
φ
= 4 MHz)
Table 8.6.1 Multi-master I
2
C-BUS Interface Functions
Item
Format
Communication mode
SCL clock frequency
φ
System clock = f(X
IN
)/2
Note :
We are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
of the I
2
C control register at address 00F9
16
) for connections between
the I
2
C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
8.6 MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I
2
C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 8.6.1 shows a block diagram of the multi-master I
2
C-BUS in-
terface and Table 8.6.1 shows multi-master I
2
C-BUS interface func-
tions.
This multi-master I
2
C-BUS interface consists of the I
2
C address reg-
ister, the I
2
C data shift register, the I
2
C clock control register, the I
2
C
control register, the I
2
C status register and other control circuits.
Fig. 8.6.1 Block Diagram of Multi-master I
2
C-BUS Interface
I
2
C address register (S0D)
b
7
b
0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RBW
N
e
c
o
l
i
i
s
e
i
n
u
i
r
m
c
a
t
i
o
n
i
t
S
d
(
e
a
S
r
t
D
i
a
l
a
A
)
Address comparator
b7
I C data shift register
b
0
D
c
c
a
o
i
t
a
t
u
n
c
r
o
i
t
l
r
I
2
C
c
l
o
c
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
l
(
S
2
)
S
y
s
t
e
m
c
l
o
c
k
(
φ
)
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
M
S
T TRX B
B
PIN
A
L
AAS AD0 L
R
B
b0
I
r
e
C
s
s
t
e
a
t
u
(
s
S
g
i
t
r
1
)
b
7
b
0
BSEL1 BSEL0
1
0
S
B
A
I
T
D
ALS
B
C
2
B
C
1 BC0
I
2
C
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
1
D
)
Bit counter
c
B
i
r
c
u
i
t
C
c
c
l
o
n
r
c
c
t
u
k
r
i
o
i
o
t
l
N
e
c
o
l
i
i
s
e
i
n
u
i
r
m
c
a
t
i
o
n
i
t
S
c
(
e
l
S
r
c
C
i
a
k
L
l
o
)
b
7
b0
ACK
A
B
C
I
K
T
FAST
Internal data bus
C
o
c
k
d
i
v
i
s
i
o
n
S
0
AL
circuit
E
S
O
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