參數(shù)資料
型號: M37281MAH-XXXSP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
中文描述: 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 16/172頁
文件大?。?/td> 1319K
代理商: M37281MAH-XXXSP
M37281MAH
XXXSP,M37281MFH
XXXSP,M37281MKH
XXXSP, M37281EKSP
Rev.1.01 2003.07.16 page 16 of 170
Fig. 8.2.5 Memory Map of Special Function Register 1 (SFR2) (2)
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
A
1
B
1
C
1
D
1
E
1
F
1
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
E
E
E
E
E
E
E
E7
16
E
E
E
0
1
1
1
2
1
3
1
4
1
5
1
6
1
6
6
6
6
6
6
6
8
1
9
1
A
1
6
6
E
E
E
E
B
1
C
1
D
1
E
1
F
1
6
6
6
6
6
6
D
D
a
a
t
t
a
a
s
s
l
l
i
i
c
c
e
e
r
r
c
c
o
o
n
n
t
t
r
r
o
o
l
l
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
(
(
D
D
S
S
C
C
1
2
)
)
A
A
T
T
T
T
T
T
I
2
C
I
2
C
address register (S0D)
-
-
i
i
i
i
i
i
D
D
m
m
m
m
m
m
e
e
e
e
e
e
d
c
c
r
r
r
r
r
r
a
o
o
t
n
n
1
2
3
4
m
m
a
v
t
(
(
(
(
o
o
s
e
r
o
T
T
T
T
d
d
h
r
l
1
2
3
4
e
e
i
s
)
)
)
)
i
e
o
n
g
i
r
s
e
t
g
e
i
s
(
t
A
e
r
(
C
A
O
D
)
r
r
D
N
)
C
Caption data register 2 (CD2)
a
p
t
i
o
n
d
a
t
a
r
e
C
p
t
i
o
n
d
a
t
a
r
e
Caption Position register (CPS)
Data slicer test register 2
Data slicer test register 1
Sync signal counter register (HC)
Clock run-in detect register (CRD)
a
t
a
c
l
o
c
k
p
o
s
i
t
i
o
a
p
t
i
o
n
d
a
t
a
r
e
g
i
s
t
e
r
1
(
C
D
1
)
t
r
r
e
e
r
g
g
g
i
i
s
s
i
t
t
e
e
t
e
r
r
r
1
2
(
S
(
(
T
T
0
M
M
)
1
2
)
)
f
e
s
I
2
C
I
2
C
clock control register (S2)
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
S
1
D
)
I
Interrupt request
register 2 (IREQ2)
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
(
I
R
E
Q
1
)
i
i
s
s
t
t
e
e
r
r
1
2
(
(
I
I
C
C
O
O
N
N
1
2
)
)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
M
)
I
2
C
status register (S1)
I
S
F
R
1
a
r
e
a
(
a
d
d
r
e
s
s
e
s
E
0
1
6
t
o
<
B
F
F
1
i
t
6
)
a
l
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
Bit allocation
State immediately after reset
0 b
:
:
F
(
F
(
i
x
o
t
n
o
t
t
h
i
s
b
i
t
i
t
t
t
o
o
0
1
)
d
o
w
r
e
:
l
o
c
a
t
i
o
n
>
<
State immediately after reset
>
0
:
1
i
m
m
e
d
Function bit
:
N
o
f
u
n
c
t
i
o
n
b
i
t
i
x
o
t
n
o
t
t
h
i
s
b
i
t
i
t
t
t
o
o
1
0
)
d
o
w
r
e
N
a
m
e
:
:
0
immediately after reset
i
a
t
: Indeterminate immediately
after reset
1
e
l
y
a
f
t
e
r
r
e
s
e
t
1
0
C
a
g
g
i
i
s
s
t
t
e
e
r
r
3
4
(
(
C
C
D
D
3
4
)
)
D
n
r
e
g
i
s
t
e
r
(
D
P
S
)
b7
7
b
0
TM20
TM21
T
M
2
2
T
M
2
3
TM24
TM10
TM11
T
M
1
2
T
M
1
3
TM14
CM2
M
3
TM1R
TM2R
T
R
T
M
4
R
OSDR
V
S
C
R
ADR
ICK0
IN1R
DSR
SIOR
M
I
O
TM1E
IN
1
TM2E
S
T
3
E
TM4E
O
S
D
E
V
S
C
E
E
D
E
S
E
IN2E
T
M
2
5
FF
16
0
FF
16
0
00
16
7
1
6
7
1
6
T
M
1
5
T
M
M
1
6
TM17
M
T
2
6
T
2
7
SAD0
D
S
A
D
1
S
A
D
2
SAD3
S
A
D
4
SAD5
R
S
A
D
6
RBW
R
L
B
A
0
AAS
AL
PIN
BB
0
S
A
FAST
MODE
T
X
MST
BC0
BC1
BC2
ESO
ALS
BSEL0
C
B
I
BSEL1
CCR0
0
CCR1
0
CCR2
CCR3
1
CCR4
1
ACK
M
1
0
1
6
0
00
16
3
0
1
C
1
6
CKR
IICR
T
M
5
6
R
ADE
CKE
IICE
T
M
5
6
E
T
M
5
6
S
C
7
CM5
C
M
6
ADIN0
ADIN1
ADIN2
ADVREF
ADSTR
1
B
I
D
T
00
16
00
16
0
1
6
00
16
DSC10
S
C
D
L
D
S
C
1
1
D
S
C
1
2
D
2
0
D
D
S
C
2
3
D
S
C
2
4
D
S
C
2
5
CRD3
CRD4
CRD5
P
C
R
D
6
CRD7
P
DPS3
DPS4
D
S
5
D
P
S
6
D
S
7
CPS0
CPS3
CPS4
00
16
00
16
CPS5
CPS1
CPS2
CPS6
CPS7
HC0
HC3
HC4
HC5
HC1
HC2
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
6
C
D
H
1
0
C
D
H
1
3
CDH14
5
C
D
H
1
CDH11
2
C
D
H
1
C
D
H
1
6
C
D
H
1
7
C
1
0
C
L
1
3
CDL14
CDL15
CDL11
CDL12
C
D
L
1
6
CDL17
00
16
0
1
6
00
16
0
0
1
6
00
16
00
16
00
16
0
1
6
D1
D2
D3
D4
D5
D6
D7
D0
0
0
0
0
0
0
0
0
0
0
0
0
A
K
T
0
C
D
H
2
0
C
D
H
2
3
CDH24
5
C
D
H
2
CDH21
2
C
D
H
2
C
D
H
2
6
C
D
H
2
7
CDL20
CDL23
CDL24
CDL25
CDL21
CDL22
CDL26
CDL27
0
0
1
9
1
6
0
0
0
0
1
0
6
6
0
B
a
n
k
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
B
K
)
BK0
B
K
3
B
K
1
B
K
2
BK6
BK7
0
0
0
0
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