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參數(shù)資料
| 型號(hào)： | M37274EFSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, MICROCONTROLLER, PDIP52 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-52 |
| 文件頁數(shù)： | 123/147頁 |
| 文件大小： | 2042K |
| 代理商： | M37274EFSP |
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77
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
(5) Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchro-
nizing signal waveform of interlacing system. The dot line 0 or 1 (re-
fer to Figure 79) corresponding to the field is displayed alternately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
69) in the microcomputer and then comparing this time with the time
of the previous field. When the time is longer than the comparing
time, it is regarded as even field. When the time is shorter, it is re-
garded as odd field
The contents of this field can be read out by the field determination
flag (bit 7 of the I/O polarity control register at address 021716). A dot
line is specified by bit 6 of the I/O polarity control register (refer to
Figure 79).
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 6.
Fig. 78. I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
I/O polarity control register (PC) [Address 021716]
B
Name
Functions
After reset R W
I/O Polarity Control Register
0HSYNC input polarity
switch bit (PC0)
0 : Positive polarity input
1 : Negative polarity input
0
1
0 : Positive polarity input
1 : Negative polarity input
0
2
R, G, B output polarity
switch bit (PC2)
0 : Positive polarity output
1 : Negative polarity output
0
3
0
VSYNC input polarity
switch bit (PC1)
RW
R—
Note: Refer to Figure 79.
0 : “
” at even field
“
” at odd field
1 : “
” at even field
“
” at odd field
4
OUT1 output polarity
switch bit (PC4)
0 : Positive polarity output
1 : Negative polarity output
0
5
OUT2 output polarity
switch bit (PC5)
0 : Positive polarity output
1 : Negative polarity output
0
6
Display dot line selection
bit (PC6) (See note)
0
7
Field determination flag
(PC7)
0 : Even field
1 : Odd field
1
RW
R—
Fix this bit to "0".
0
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