參數(shù)資料
型號： M37274EFSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, MICROCONTROLLER, PDIP52
封裝： 0.600 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-52
文件頁數(shù)： 106/147頁
文件大小： 2042K
代理商： M37274EFSP
61
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
(9) START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in Figure
52 and Table 9. Only when the 3 conditions of Table 9 are satisfied,
a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated
to the CPU.
(8) STOP Condition Generation Method
When the ES0 bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition genera-
tion timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 51 for
the STOP condition generation timing diagram, and Table 8 for the
START condition/STOP condition generation timing table.
Fig. 59. STOP Condition Generation Timing Diagram
Fig. 60. START Condition/STOP Condition Detect Timing
Diagram
Standard Clock Mode
6.5
s (26 cycles) < SCL
release time
3.25
s (13 cycles) < Setup time
3.25
s (13 cycles) < Hold time
High-speed Clock Mode
1.0
s (4 cycles) < SCL
release time
0.5
s (2 cycles) < Setup time
0.5
s (2 cycles) < Hold time
Table 9. START Condition/STOP Condition Detect Conditions
Table 8. START Condition/STOP Condition Generation Timing
Table
Item
Setup time
Hold time
Set/reset time
for BB flag
Standard Clock Mode
5.0
s (20 cycles)
5.0
s (20 cycles)
3.0
s (12 cycles)
High-speed Clock Mode
2.5
s (10 cycles)
2.5
s (10 cycles)
1.5
s (6 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses de-
notes the number of
φ cycles.
Note: Absolute time at
φ = 4 MHz. The value in parentheses de-
notes the number of
φ cycles.
I2C status register
write signal
Reset time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Hold time
Setup
time
SCL
SDA
(START condition)
SDA
(STOP condition)
SCL release time
Hold time
Setup
time
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