- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69013 > M37274EFSP 8-BIT, OTPROM, MICROCONTROLLER, PDIP52 PDF資料下載
參數(shù)資料
| 型號： | M37274EFSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, MICROCONTROLLER, PDIP52 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-52 |
| 文件頁數(shù)： | 107/147頁 |
| 文件大小： | 2042K |
| 代理商： | M37274EFSP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁當(dāng)前第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁
62
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
(10) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order
7-bit slave address stored in the I2C address register (address
00F716). At the time of this comparison, address comparison of
the RBW bit of the I2C address register (address 00F716) is not
made. For the data transmission format when the 7-bit address-
ing format is selected, refer to Figure 61, (1) and (2).
10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “1.” An address compari-
son is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I2C address
register (address 00F716). At the time of this comparison, an ad-
dress comparison between the RBW bit of the I2C address regis-
__
ter (address 00F716) and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
__
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I2C status register (address 00F816) is set to “1.” After
the second-byte address data is stored into the I2C data shift register
(address 00F616), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
the I2C address register (address 00F716) to “1” by software. This
__
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I2C address register (address 00F716). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 61, (3) and (4).
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 00FA16).
Set “1016” in the I2C status register (address 00F816) and hold
the SCL at the HIGH.
Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
Set the address data of the destination of transmission in the high-
order 7 bits of the I2C data shift register (address 00F616) and set
“0” in the least significant bit.
Set “F016” in the I2C status register (address 00F816) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I2C data shift register (address 00F616).
At this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step
.
Set “D016” in the I2C status register (address 00F816). After this,
if ACK is not returned or transmission ends, a STOP condition will
be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
Set the no ACK clock mode and SCL = 400 kHz by setting “2516”
in the I2C clock control register (address 00FA16).
Set “1016” in the I2C status register (address 00F816) and hold
the SCL at the HIGH.
Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
When a START condition is received, an address comparison is
made.
When all transmitted addresses are “0” (general call) :
AD0 of the I2C status register (address 00F816) is set to “1” and
an interrupt request signal occurs.
When the transmitted addresses match the address set in :
AAS of the I2C status register (address 00F816) is set to “1” and
an interrupt request signal occurs.
In the cases other than the above :
AD0 and AAS of the I2C status register (address 00F816) are
set to “0” and no interrupt request signal occurs.
Set dummy data in the I2C data shift register (address 00F616).
When receiving control data of more than 1 byte, repeat step .
When a STOP condition is detected, the communication ends.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37274EFSP | 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52 |
| M37274MA-XXXSP | 8-BIT, MROM, MICROCONTROLLER, PDIP52 |
| M37373M8-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52 |
| M37409M2-XXXFP | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP56 |
| M37413E6HXXXFP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37274ERSS | 功能描述:EMULATION MCU/8BIT CMOS EMULATIO RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關(guān)產(chǎn)品:1-Wire? 設(shè)備 產(chǎn)品目錄頁面:1429 (CN2011-ZH PDF) |
| M37274MA | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37274MA-052SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37274MA-053SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
| M37274MA-082SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。