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參數(shù)資料
| 型號(hào)： | M36WT864T10ZA6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| 中文描述： | 64兆位4Mb的x16插槽，多銀行，突發(fā)閃存和8兆位的SRAM為512k x16，內(nèi)存產(chǎn)品多 |
| 文件頁(yè)數(shù)： | 18/92頁(yè) |
| 文件大?。?/td> | 624K |
| 代理商： | M36WT864T10ZA6T |
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M36WT864TF, M36WT864BF
18/92
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits 4 and 5 are set and the
command aborts. Erase aborts if Reset turns to
V
IL
. As data integrity cannot be guaranteed when
the Erase operation is aborted, the block must be
erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register mode un-
til a Read Array, Read CFI Query or Read Elec-
tronic Signature command is issued.
During Erase operations the bank containing the
block being erased will only accept the Read Ar-
ray, Read Status Register, Read Electronic Signa-
ture, Read CFI Query and the Program/Erase
Suspend command, all other commands will be ig-
nored. Refer to Dual Operations section for de-
tailed information about simultaneous operations
allowed in banks not being erased. Typical Erase
times are given in Table 14, Program, Erase
Times and Program/Erase Endurance Cycles.
See Appendix C, Figure 32, Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
for using the Block Erase command.
Bank Erase Command
The Bank Erase command can be used to erase a
bank. It sets all the bits within the selected bank to
’1’. All previous data in the bank is lost. The Bank
Erase command will ignore any protected blocks
within the bank. If all blocks in the bank are pro-
tected then the Bank Erase operation will abort
and the data in the bank will not be changed. The
Status Register will not output any error.
Two Bus Write cycles are required to issue the
command.
I
The first bus cycle sets up the Bank Erase
command.
I
The second latches the bank address in the
internal state machine and starts the Program/
Erase Controller.
If the second bus cycle is not Write Bank Erase
Confirm (D0h), Status Register bits SR4 and SR5
are set and the command aborts. Erase aborts if
Reset turns to V
IL
. As data integrity cannot be
guaranteed when the Erase operation is aborted,
the bank must be erased again.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read. At the end of the operation the
bank will remain in Read Status Register mode un-
til a Read Array, Read CFI Query or Read Elec-
tronic Signature command is issued.
During Bank Erase operations the bank being
erased will only accept the Read Array, Read Sta-
tus Register, Read Electronic Signature and Read
CFI Query command, all other commands will be
ignored. A Bank Erase operation cannot be sus-
pended.
Refer to Dual Operations section for detailed infor-
mation about simultaneous operations allowed in
banks not being erased. Typical Erase times are
given in Table 14, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
Program Command
The memory array can be programmed word-by-
word. Only one Word in one bank can be pro-
grammed at any one time. Two bus write cycles
are required to issue the Program Command.
I
The first bus cycle sets up the Program
command.
I
The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
After programming has started, read operations in
the bank being programmed output the Status
Register content.
During Program operations the bank being pro-
grammed will only accept the Read Array, Read
Status Register, Read Electronic Signature, Read
CFI Query and the Program/Erase Suspend com-
mand. Refer to Dual Operations section for de-
tailed information about simultaneous operations
allowed in banks not being programmed. Typical
Program times are given in Table 14, Program,
Erase Times and Program/Erase Endurance Cy-
cles.
Programming aborts if Reset goes to V
IL
. As data
integrity cannot be guaranteed when the program
operation is aborted, the memory location must be
reprogrammed.
See Appendix C, Figure 28, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Block Erase operation. A
Bank Erase operation cannot be suspended.
One bus write cycle is required to issue the Pro-
gram/Erase command. Once the Program/Erase
Controller has paused bits SR7, SR6 and/ or SR2
of the Status Register will be set to ‘1’. The com-
mand can be addressed to any bank.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read Array (cannot read the suspended block),
Read Status Register, Read Electronic Signature
and Read CFI Query commands. Additionally, if
the suspend operation was Erase then the Clear
status Register, Program, Block Lock, Block Lock-
Down or Block Unlock commands will also be ac-
cepted. The block being erased may be protected
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M36WT864TF | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864B85ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864T70ZA6T | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864TFZA | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864BFZA | 64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M36WT864T70ZA6T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864T85ZA6T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864TF | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
| M36WT864TF70ZA6T | 功能描述:組合存儲(chǔ)器 64M (4Mx16) 70ns RoHS:否 制造商:Microchip Technology 組織:512 K x 16 電源電壓-最大: 電源電壓-最小: 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:LFBGA-48 封裝:Tray |
| M36WT864TFZA | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:64 Mbit 4Mb x16, Multiple Bank, Burst Flash Memory and 8 Mbit 512K x16 SRAM, Multiple Memory Product |
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