參數(shù)資料
型號: M36W832BE85ZA1S
廠商: NUMONYX
元件分類: 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA66
封裝: 12 X 8 MM, 0.80 MM PITCH, LFBGA-66
文件頁數(shù): 31/64頁
文件大?。?/td> 897K
代理商: M36W832BE85ZA1S
37/64
M36W832TE, M36W832BE
Table 20. SRAM Read AC Characteristics
Note: 1. Sampled only. Not 100% tested.
Figure 17. SRAM Write AC Waveforms, E1S or E2S Controlled
Note: 1. DQ0-DQ15 are high impedance if GS = VIH.
2. If E1S or E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
Symbol
Alt
Parameter
SRAM
Unit
Min
Max
tAVAV
tRC
Read Cycle Time
70
ns
tAVQV
tACC
Address Valid to Output Valid
70
ns
tAXQX
tOH
Address Transition to Output Transition
10
ns
tE1HQZ
tE2LQZ
tCHZ1
Chip Enable 1 High to Output Hi-Z
25
ns
tE1LQV
tE2HQV
tACS1
Chip Enable 1 Low or Chip Enable 2 High to Output Valid
70
ns
tE1LQX
tE2HQX
tCLZ1
Chip Enable 1 Low to Output Transition
10
ns
tGHQZ
tOHZ
Output Enable High to Output Hi-Z
25
ns
tGLQV
tOE
Output Enable Low to Output Valid
35
ns
tGLQX
tOLZ
Output Enable Low to Output Transition
5
ns
tPD
(1)
Chip Enable 1 High or Chip Enable 2 Low to Power Down
70
ns
tPU
(1)
Chip Enable 1 Low or Chip Enable 2 High to Power Up
0
ns
AI07966
tAVAV
tE1HAX
tDVE1H
tDVE2L
INPUT VALID
A0-A18
E1S
WS
DQ0-DQ15
ADDRESS VALID
E2S
tAVE1H
tAVE2L
tWLE1H
tWLE2L
tE1HDZ
tE2LDZ
tAVE1L
tE2HE2L
tE1LE1H
tAVE2H
tE2LAX
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