參數(shù)資料
型號(hào): M36W432BG85ZA6T
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product
中文描述: 32兆位的2Mb x16插槽,開機(jī)區(qū)塊快閃記憶體和4兆位的256Kb x16的SRAM,多個(gè)存儲(chǔ)產(chǎn)品
文件頁(yè)數(shù): 35/57頁(yè)
文件大小: 418K
代理商: M36W432BG85ZA6T
35/57
M36W432T, M36W432B
Table 20. SRAM Write AC Characteristics
Note: 1. t
AS
is measured from the address valid to the beginning of write.
2. t
WR
is measured from the end or write to the address change. t
WR
applied in case a write ends as E1S or WS going high.
3. t
CW
is measured from E1S going low end of write.
4. A Write occurs during the overlap (t
WP
) of low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-
liest transition when E1S goes high and WS goes high. The t
WP
is measured from the beginning of write to the end of write.
Symbol
Alt
Parameter
SRAM
Unit
Min
Max
t
AVAV
t
WC
Write Cycle Time
70
ns
t
AVE1L
t
AS(1)
Address Valid to Chip Enable 1 Low
0
ns
t
AVE2H
t
AS(1)
Address Valid to Chip Enable 2 High
0
ns
t
AVWH
t
AW
Address Valid to Write Enable High
60
ns
t
AVWL
t
AS(1)
Address Valid to Write Enable Low
0
ns
t
BLWH
t
BW
UBS, LBS Valid to End of Write
60
ns
t
DVE1H
t
DW
Input Valid to Chip Enable 1 High
30
ns
t
DVE2L
t
DW
Input Valid to Chip Enable 2 Low
30
ns
t
DVWH
t
DW
Input Valid to Write Enable High
30
ns
t
E1HAX
t
WR(2)
Chip Enable 1 High to Address Transition
0
ns
t
E1LWH
,
t
E2HWH
t
CW(3)
Chip Select to End of Write
60
ns
t
E2LAX
t
WR(2)
Chip Enable 2 Low to Address Transition
0
ns
t
GHQZ
t
GHZ
Output Enable High to Output Hi-Z
25
ns
t
WHAX
t
WR(2)
Write Enable High to Address Transition
0
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
ns
t
WHQX
t
OW
Write Enable High to Output Transition
10
ns
t
WLQZ
t
WHZ
Write Enable Low to Output Hi-Z
25
ns
t
WLWH
t
WP(4)
Write Enable Pulse Width
50
ns
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