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參數(shù)資料
| 型號： | M36D0R6040T0ZAIT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package |
| 中文描述： | 64兆位（4Mb的x16插槽，多銀行，頁）閃存和16兆位（最快1Mb × 16）移動存儲芯片，多芯片封裝 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 329K |
| 代理商： | M36D0R6040T0ZAIT |
M36D0R6040T0, M36D0R6040B0
6/18
SIGNAL DESCRIPTIONS
See
Figure 2., Logic Diagram
and
Table 1., Signal
Names
, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19).
Addresses
are common inputs for the Flash Memory and
PSRAM components. The Address Inputs select
the cells in the memory array to access during Bus
Read operations. During Bus Write operations
they control the commands sent to the Command
Interface of the Flash memory internal state ma-
chine and they select the cells to access in the
PSRAM.
The Flash memory is accessed through the Chip
Enable signal (E
F
) and through the Write Enable
(W
F
) signal, while the PSRAM is accessed
through two Chip Enable signals (E1
P
and E2
P
)
and the Write Enable signal (W
P
).
Address Inputs (A20-A21).
Addresses A20-A21
are inputs for the Flash Memory component only.
The Flash Memory is accessed through the Chip
Enable signals (
E
F
) and through the Write Enable
(W
F
) signal.
Data Input/Output (DQ0-DQ15).
The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (E
F
).
The Chip Enable in-
puts activate the memory control logics, input buff-
ers, decoders and sense amplifiers. When Chip
Enable is Low, V
IL
, and
Reset is High, V
IH
, the de-
vice is in active mode. When Chip Enable is at V
IH
the Flash memory is deselected, the outputs are
high impedance and the power consumption is re-
duced to the standby level.
Flash Output Enable (G
F
).
The Output Enable
pins control data outputs during Flash memory
Bus Read operations.
Flash Write Enable (
W
F
).
The
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP
F
).
Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, V
IL
,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, V
IH
, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR064F(T/B) datasheet).
Flash Reset (RP
F
).
The Reset input provides a
hardware reset of the memory. When Reset is at
V
IL
, the memory is in Reset mode: the outputs are
A0-A19
Write
Enable
high impedance and the current consumption is
reduced to the Reset Supply Current I
DD2
. Refer to
Table 7., Flash Memory DC Characteristics - Cur-
rents
, for the value of I
DD2
. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at V
IH
, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V
RPH
(refer to
Table 8., Flash Memory DC Characteris-
tics - Voltages
).
PSRAM Chip Enable (E1
P
).
When
(Low), the Chip Enable, E1
P
, activates the memo-
ry state machine, address buffers and decoders,
allowing Read and Write operations to be per-
formed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
PSRAM Chip Enable (E2
P
).
The Chip Enable,
E2
P
, puts the device in Deep Power-down mode
when it is driven Low. This is the lowest power
mode.
PSRAM Output Enable (G
P
).
The Output En-
able, G
P
, provides a high speed tri-state control,
allowing fast read/write cycles to be achieved with
the common I/O data bus.
PSRAM Write Enable (W
P
).
The Write Enable,
W
P
, controls the Bus Write operation of the mem-
ory’s Command Interface.
PSRAM Upper Byte Enable (UB
P
).
The Upper
Byte Enable, UB
P
, gates the data on the Upper
Byte Data Inputs/Outputs (DQ8-DQ15) to or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LB
P
).
The Lower
Byte Enable, LB
P
, gates the data on the Lower
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
V
DDF
Supply Voltage.
V
DDF
provides the power
supply to the internal core of the Flash memory
component. It is the main power supplies for all
Flash memory operations (Read, Program and
Erase).
V
DDP
Supply Voltage.
The V
DDP
Supply Volt-
age supplies the power for all operations (Read or
Write) and for driving the refresh logic, even when
the device is not being accessed.
V
PPF
Program Supply Voltage.
V
PPF
is both a
Flash Memory control input and a Flash Memory
power supply pin. The two functions are selected
by the voltage range applied to the pin.
asserted
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