參數(shù)資料
型號： M36D0R6040T0ZAIT
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
中文描述： 64兆位（4Mb的x16插槽，多銀行，頁）閃存和16兆位（最快1Mb × 16）移動存儲芯片，多芯片封裝
文件頁數(shù)： 1/18頁
文件大?。?/td> 329K
代理商： M36D0R6040T0ZAIT
1/18
December 2004
M36D0R6040T0
M36D0R6040B0
64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory
and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
FEATURES SUMMARY
MULTI-CHIP PACKAGE
–
1 die of 64 Mbit (4Mb x 16) Flash Memory
–
1 die of 16 Mbit (1Mb x 16) Pseudo SRAM
SUPPLY VOLTAGE
–
V
DDF
= V
DDP
= 1.7V to 1.95V
LOW POWER CONSUMPTION
ELECTRONIC SIGNATURE
–
Manufacturer Code: 20h
–
Device Code (Top Flash Configuration),
M36D0R6040T0: 8810h
–
Device Code (Bottom Flash
Configuration), M36D0R6040B0: 8811h
PACKAGE
–
Compliant with Lead-Free Soldering
Processes
–
Lead-Free Versions
FLASH MEMORY
PROGRAMMING TIME
–
8μs by Word typical for Fast Factory
Program
–
Double/Quadruple Word Program option
–
Enhanced Factory Program options
MEMORY BLOCKS
–
Multiple Bank Memory Array: 4 Mbit
Banks
–
Parameter Blocks (Top location)
ASYNCHRONOUS READ
–
Asynchronous Page Read mode
–
Random Access: 70ns
DUAL OPERATIONS
–
Program Erase in one Bank while Read in
others
–
No delay between Read and Write
operations
BLOCK LOCKING
–
All blocks locked at Power-up
–
Any combination of blocks can be locked
–
WP
F
for Block Lock-Down
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■
■
■
■
■
■
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Figure 1. Package
■
SECURITY
–
128-bit user programmable OTP cells
–
64-bit unique device number
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM
ACCESS TIME: 70ns
LOW STANDBY CURRENT: 110μA
DEEP POWER DOWN CURRENT: 10μA
■
■
■
■
■
FBGA
Stacked TFBGA67 (ZAI)
12 x 8mm
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
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