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參數(shù)資料
| 型號(hào)： | M34556M8H-XXXFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁(yè)數(shù)： | 70/147頁(yè) |
| 文件大?。?/td> | 1087K |
| 代理商： | M34556M8H-XXXFP |
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Rev.3.02
Dec 22, 2006
page 27 of 142
REJ03B0025-0302
4556 Group
(3) Notes on External 0 interrupts
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
Depending on the input state of the D5/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure 18).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 18).
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
8
; (12)
TI1A
; Control of INT pin input is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 18 External 0 interrupt program example-1
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
When the key-on wakeup function of INT pin is not used (register
K20 = “0”), clear bits 2 and 3 of register I1 before system enters
to the power down mode. (refer to Figure 19).
LA
0
; (002)
TI1A
; Input of INT disabled ........................
DI
EPOF
POF2
; power down mode
: these bits are not used here.
Fig. 19 External 0 interrupt program example-2
Note on bit 2 of register I1
When the interrupt valid waveform of the D5/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
Depending on the input state of the D5/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure 20).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 20).
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
12
TI1A
; Interrupt valid waveform is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 20 External 0 interrupt program example-3
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| M34559G6FP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| M34559G6-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| M34570EDFP | 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M34556M8-XXXFP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34556MXH-XXXFP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34556MX-XXXFP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34559G6 | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34559G6FP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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