FUNCTIONAL BLOCK OPERATIONS
4551 Group User’s Manual
HARDWARE
1-33
Program counter (PC) ............................................................................................
Address 0 in page 0 is set to program counter.
Interrupt enable flag (INTE) ...................................................................................
Power down flag (P) ...............................................................................................
External 0 interrupt request flag (EXF0) ................................................................
Interrupt control register V1 ...................................................................................
Interrupt control register I1 ....................................................................................
Timer 1 interrupt request flag (T1F) ......................................................................
Timer 2 interrupt request flag (T2F) ......................................................................
Watchdog timer flag (WDF) ...................................................................................
Watchdog timer enable flag (WEF) .......................................................................
Timer control register W1 ......................................................................................
Timer control register W2 ......................................................................................
Timer control register W3 ......................................................................................
Clock control register MR ......................................................................................
Carrier wave selection register C1 ........................................................................
Carrier wave output control register C2 .................................................................
Carrier wave generating control flag CR ...............................................................
LCD control register L1 ..........................................................................................
LCD control register L2 ..........................................................................................
Pull-up control register PU0 ...................................................................................
General-purpose register V2 .................................................................................
Carry flag (CY) .......................................................................................................
Register A ..............................................................................................................
Register B ..............................................................................................................
Register D ..............................................................................................................
Register E ..............................................................................................................
Data pointer X ........................................................................................................
Data pointer Y ........................................................................................................
Data pointer Z ........................................................................................................
Stack pointer (SP) ..................................................................................................
(2) Internal state at reset
Table 14 shows port state at reset, and Figure 31 shows
internal state at reset (they are retained after system is
released from reset).
Name
D0–D4, D5/INT
D6/XCIN, D7/XCOUT
P00–P03
P10–P13
P20/SEG16–P23/SEG19
SEG0–SEG15
COM0–COM3
CARR
State
High impedance (Note 1)
“H” (VDD) level (Note 1)
(Notes 1, 2)
High impedance
VLC3 (VDD) level
“L” (VSS) level
Function
D0–D4, D5
D6, D7
P00–P03
P10–P13
P20–P23
SEG0–SEG15
COM0–COM3
CARR
Notes 1: Output latch is set to “1.”
2: The pull-up transistor is turned off.
Table 14 Port state at reset
The contents of timers, registers, flags and RAM except those
shown in Figure 31 are undefined, so set the initial values to
them.
000
00
0
(Interrupt disabled)
0
(Interrupt disabled)
000
0
(Prescaler stopped)
0
(Timer 1 stopped)
0
(Timer LC stopped)
100
0
011
1
0
(Carrier wave output disabled)
0
(LCD off)
1
(Port P2 selected)
000
0
000
0
000
0
000
0
!! !
000
0
000
0
!!
11
1
“!” represents undefined.
Fig. 31 Internal state at reset
! !!! !!! !