參數(shù)資料
型號(hào): M34551E8FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁(yè)數(shù): 126/155頁(yè)
文件大?。?/td> 1329K
代理商: M34551E8FP
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HARDWARE
1-60
4551 Group User’s Manual
CONTROL REGISTERS
V13
V12
V11
V10
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
Interrupt control register V1
at reset : 00002
at power down : 00002
R/W
Prescaler control bit
Prescaler dividing ratio selection bit
Timer 1 count source selection bits
Timer control register W1
W13
W12
W11
W10
at reset : 00002
at power down : 00002
0
1
0
1
R/W
Stop (prescaler state initialized)
Operating
Instruction clock (INSTCK) divided by 4
Instruction clock (INSTCK) divided by 8
Count source
Prescaler output (ORCLK)
Carrier output (CARRY)
Carrier output divided by 2 (CARRY/2)
W11
0
1
W10
0
1
0
1
Timer control register W2
at reset : 10002
at power down : – – – 02
R/W
0
1
f(XCIN)
Prescaler output (ORCLK)
W23
W22
W21
W20
Timer 2 count source selection bit
Timer 2 count value selection bits
Timer 1 control bit
W22
0
1
W21
0
1
0
1
Count source
Underflow occur every 214 count
Underflow occur every 213 count
Not available
Stop (timer 1 state retained)
Operating
0
1
Timer control register W3
at reset : 002
at power down : state retained
R/W
0
1
0
1
Bit 3 of timer 2 is output (timer 2 count source divided by 16)
System clock (STCK)
Stop (timer LC state retained)
Operating
W31
W30
Timer LC count source selection bit
Timer LC control bit
Note: “R” represents read enabled, and “W” represents write enabled.
“–” represents state retained.
CONTROL REGISTERS
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