參數(shù)資料
型號: M34551E8FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù): 151/155頁
文件大?。?/td> 1329K
代理商: M34551E8FP
APPLICATION
2.3 Timers
2-17
4551 Group User’s Manual
2.3 Timers
The 4551 Group has an 8-bit timer with a reload register, a 4-bit timer and the 14-bit fixed dividing frequency
timer which has the watchdog timer function.
This section describes individual types of timers, related registers, application examples using timers and
notes.
2.3.1 Timer functions
(1)
Timer 1
s Timer operation
s Carrier wave output auto-control function
(Refer to section “2.4 Carrier generating circuit” for details.)
(2)
Timer 2
s Timer operation
(Timer 2 has the function to return from clock operation mode (POF instruction execution))
s Watchdog function
Watchdog timer provides a method to reset the system when a program runs wild.
When the WRST instruction is executed after system is released from reset, in this time, the
watchdog timer starts operating. System reset is performed if the WRST instruction is not performed
while timer 2 counts 213.
(3)
Timer LC
s LCD frame clock generating
2.3.2 Related registers
(1)
Interrupt control register V1
The timer 1 interrupt enable bit is assigned to the bit 2, and the timer 2 interrupt enable bit is
assigned to the bit 3.
Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register A.
Table 2.3.1 shows the interrupt control register V1.
Table 2.3.1 Interrupt control register V1
Interrupt control register V1
at reset : 00002
at power down : 00002
R/W
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
V13
V12
V11
V10
0
1
0
1
0
1
0
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When timer is used, V10 is not used.
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