參數(shù)資料
型號： M34524MC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù)： 80/161頁
文件大?。?/td> 1199K
代理商： M34524MC-XXXFP
Rev.2.00
Jul 27, 2004
page 25 of 159
REJ03B0091-0200Z
4524 Group
Fig. 16 Interrupt sequence
T1F,T2F,T3F,T4F
T5F,ADF,SIOF
INT0,INT1
EXF0,EXF1
T
1
T
2
T
3
T
1
T
2
T
3
T
2
T
3
T
1
T
1
T
2
T
3
T
1
T
2
q
When
an
interrupt
request
flag
is
set
after
its
interrupt
is
enabled
(Note
1)
System
clock
(STCK)
The
program
starts
from
the
interrupt
address.
Interrupt
enabled
state
1
machine
cycle
EI
instruction
execution
cycle
Interrupt
enable
flag
(INTE)
Retaining
level
of
system
clock
for
4
periods
or
more
is
necessary.
Interrupt
disabled
state
External
interrupt
Timer
1,
Timer
2,
Timer
3,
Timer
4,
Timer
5,
A/D
and
Serial
I/O
interrupts
Interrupt
activated
condition
is
satisfied.
Notes
1:
The
address
to
be
executed
when
returning
to
the
main
routine
is
stacked
to
the
last
machine
cycle.
2:
The
cycles
are
as
follows
according
to
the
executed
instruction
at
the
time
when
each
interrupt
activated
condition
is
satis
fied.
On
execution
of
one-cycle
instruction:
Interrupt
occurs
after
2
machine
cycles.
On
execution
of
two-cycle
instruction:
Interrupt
occurs
after
3
machine
cycles.
On
execution
of
three-cycle
instruction:
Interrupt
occurs
after
3
machine
cycles.
Flag
cleared
2
to
3
machine
cycles
(Notes
1,
2)
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