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參數(shù)資料
| 型號： | M34524MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 77/161頁 |
| 文件大?。?/td> | 1199K |
| 代理商： | M34524MC-XXXFP |
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Rev.2.00
Jul 27, 2004
page 22 of 159
REJ03B0091-0200Z
4524 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.
An interrupt activated condition is satisfied (request flag = “1”)
Interrupt enable bit is enabled (“1”)
Interrupt enable flag is enabled (INTE = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every inter-
rupt enable/disable. Interrupts are enabled when INTE flag is set to
“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag
is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the cor-
responding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;
an interrupt occurs, or
the next instruction is skipped with a skip instruction.
Each interrupt request flag is set to “1” when the activated condi-
tion is satisfied even if the interrupt is disabled by the INTE flag or
its interrupt enable bit. Once set, the interrupt request flag retains
set until it is cleared to “0” by the interrupt occurrence or the skip
instruction.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set to “1” when the inter-
rupt disable state is released, the interrupt priority level is as
follows shown in Table 3.
Table 3 Interrupt sources
Activated condition
Level change of
INT0 pin
Level change of
INT1 pin
Timer 1 underflow
Timer 2 underflow
Timer 3 underflow
Timer 5 underflow
Completion of
A/D conversion
Timer 4 underflow
or completion of
serial I/O transmit/
receive
Priority
level
1
2
3
4
5
6
7
8
Interrupt name
External 0 interrupt
External 1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 5 interrupt
A/D interrupt
Timer 4 interrupt or
Serial I/O interrupt
(Note)
Interrupt
request flag
EXF0
EXF1
T1F
T2F
T3F
T5F
ADF
T4F
SIOF
Interrupt name
External 0 interrupt
External 1 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 5 interrupt
A/D interrupt
Timer 4 interrupt
Serial I/O interrupt
Table 5 Interrupt enable bit function
Occurrence of interrupt
Enabled
Disabled
Skip instruction
Invalid
Valid
Interrupt enable bit
1
0
Interrupt
address
Address 0
in page 1
Address 2
in page 1
Address 4
in page 1
Address 6
in page 1
Address 8
in page 1
Address A
in page 1
Address C
in page 1
Address E
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip in-
struction
Skip instruction
SNZ0
SNZ1
SNZT1
SNZT2
SNZT3
SNZT5
SNZAD
SNZT4
SNZSI
Interrupt
nable bit
V10
V11
V12
V13
V20
V21
V22
V23
Note: Timer 4 interrupt or serial I/O interrupt can be selected by the timer 4,
serial I/O interrupt source selection bit (I30).
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