- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98005 > M34524MC-XXXFP 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | M34524MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 79/161頁 |
| 文件大?。?/td> | 1199K |
| 代理商： | M34524MC-XXXFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當前第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁
Rev.2.00
Jul 27, 2004
page 24 of 159
REJ03B0091-0200Z
4524 Group
(6) Interrupt control registers
Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
Interrupt control register V2
The timer 3, timer 5, A/D, Timer 4 and serial I/O interrupt enable
bit is assigned to register V2. Set the contents of this register
through register A with the TV2A instruction. The TAV2 instruction
can be used to transfer the contents of register V2 to register A.
Table 6 Interrupt control registers
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instruction.
3: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source selection bit (I30).
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10–V13, V20–V23), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the ma-
chine cycle in which all three conditions are satisfied. The interrupt
occurs after 3 machine cycles when the interrupt conditions are
satisfied on execution of two-cycle instructions or three-cycle in-
structions. (Refer to Figure 16).
Interrupt disabled (SNZT4, SNZSI instruction is valid)
Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 2)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
Interrupt disabled (SNZT5 instruction is valid)
Interrupt enabled (SNZT5 instruction is invalid) (Note 2)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid) (Note 2)
V13
V12
V11
V10
V23
V22
V21
V20
Timer 4, serial I/O interrupt enable bit (Note 3)
A/D interrupt enable bit
Timer 5 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register V2
at power down : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid) (Note 2)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
0
1
0
1
0
1
0
1
at power down : 00002
at reset : 00002
R/W
TAV1/TV1A
R/W
TAV2/TV2A
I30
Timer 4, serial I/O interrupt source selection
bit
Interrupt control register I3
R/W
TAI3/TI3A
at power down : state retained
at reset : 02
Timer 4 interrupt valid, serial I/O interrupt invalid
Serial I/O interrupt valid, timer 4 interrupt invalid
0
1
Interrupt control register I3
The timer 4, serial I/O interrupt source selection bit is assigned to
register I3. Set the contents of this register through register A
with the TI3A instruction. The TAI3 instruction can be used to
transfer the contents of register I3 to register A.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M34550E8FS | 4-BIT, UVPROM, 1.6 MHz, MICROCONTROLLER, CQCC80 |
| M34551E8-XXXFP | 4-BIT, OTPROM, MICROCONTROLLER, PQFP48 |
| M34554M8-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| M34554MC-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| M34571G6FP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3452-C09K1 | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING TRANSISTOR |
| M3452-C125K2 | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING TRANSISTOR |
| M3452-C125K2,A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING TRANSISTOR |
| M3452-C150B7 | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING TRANSISTOR |
| M3452-C150B7-A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING TRANSISTOR |
發(fā)布緊急采購，3分鐘左右您將得到回復。