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參數(shù)資料
| 型號： | M34524EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 56/66頁 |
| 文件大?。?/td> | 1936K |
| 代理商： | M34524EDFP |
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Rev.1.04
Aug 23, 2007
Page 61 of 146
REJ03B0188-0104
4559 Group
CLOCK CONTROL
The clock control circuit consists of the following circuits.
On-chip oscillator (internal oscillator)
Ceramic resonator
RC oscillation circuit
Quartz-crystal oscillation circuit
Multi-plexer (clock selection circuit)
Frequency divider
Internal clock generating circuit
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 59 shows the structure of the clock control circuit.
The 4559 Group operates by the on-chip oscillator clock
(f(RING)) which is the internal oscillator after system is released
from reset.
Also, the ceramic resonator or the RC oscillation can be used for
the main clock (f(XIN)) of the 4559 Group.
The quartz-crystal oscillator can be used for sub-clock (f(XCIN)).
Fig 59. Clock control circuit structure
MR3, MR2
00
01
10
11
Q S
R
Q
R
Timer 3 underflow signal
EPOF instruction +
XCOUT
XCIN
R
EPOF instruction +
10
MR1,MR0
11
System clock (STCK)
Instruction clock
(INSTCK)
Multi-
plexer
Quartz-crystal
oscillation
On-chip oscillator
(internal oscillator)
XOUT
XIN
Ceramic
resonance
RC oscillation
Internal clock
generating circuit
(divided by 3)
RG1
01
RG0
RG2
Divided by 2
Divided by 4
Divided by 8
Division circuit
S
QS
CRCK instruction
Internal reset signal
Key-on wakeup signal
POF instruction
POF2 instruction
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相關(guān)代理商/技術(shù)參數(shù) |
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| M34524M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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| M3452-C125K2,A | 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING TRANSISTOR |
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