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參數(shù)資料
| 型號： | M34524EDFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 10/66頁 |
| 文件大?。?/td> | 1936K |
| 代理商： | M34524EDFP |
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Rev.1.04
Aug 23, 2007
Page 18 of 146
REJ03B0188-0104
4559 Group
FUNCTION BLOCK OPERATIONS
CPU
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as
4-bit data addition, comparison, AND operation, OR operation,
and bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 12).
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 13).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and register
A as the low-order 4 bits (Figure 14).
Register E is undefined after system is released from reset and
returned from the power down mode. Accordingly, set the initial
value.
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A
and is used as a pointer within the specified page when the TABP
p, BLA p, or BMLA p instruction is executed (Figure 15).
Also, when the TABP p instruction is executed at UPTF flag =
“1”, the high-order 2 bits of ROM reference data is stored to the
low-order 2 bits of register D, the high-order 1 bit of register D is
“0”.
When the TABP p instruction is executed at UPTF flag = “0”, the
contents of register D remains unchanged. The UPTF flag is set
to “1” with the SUPT instruction and cleared to “0” with the
RUPT instruction.
The initial value of UPTF flag is “0”.
Register D is undefined after system is released from reset and
returned from the power down mode. Accordingly, set the initial
value.
Fig 12. AMC instruction execution example
Fig 13. RAR instruction execution example
Fig 14. Registers A, B and register E
Fig 15. TABP p instruction execution example
(CY)
<Result>
(M(DP))
(A)
Addition
ALU
<Carry>
<Clear>
RC instruction
<Set>
SC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
TABE instruction
TEAB instruction
A3 A2 A1 A0
Register A
TAB instruction
E3 E2 E1 E0
E7 E6 E5 E4
B3 B2 B1 B0
Register B
Register E
A3 A2 A1 A0
Register A
TBA instruction
B3 B2 B1 B0
Register B
A3 A2 A1 A0
DR2 DR1 DR0
PCL
Register A (4)
Low-order 2 bits
Register D (3)
Register B (4)
Middle-order 2 bits
ROM
Field value p
The contents
of register D
Specifying address
TABP p
instruction
p3
p2
p1
p0
p6
p5
p4
PCH
84
0
The contents
of register A
High-order 2 bits
Flag UPTF = 1;
High-order 2 bits of reference data is transferred to the low-order 2
bits of register D.
“0” is stored to the high-order 1 bit of register D.
Flag UPTF = 0;
Data is not transferred to register D.
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