參數(shù)資料
型號: M34524EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 46/66頁
文件大?。?/td> 1936K
代理商: M34524EDFP
Rev.1.04
Aug 23, 2007
Page 51 of 146
REJ03B0188-0104
4559 Group
(4) Internal state at reset
Figure 51 and 52 shows internal state at reset (they are the same
after system is released from reset). The contents of timers,
registers, flags and RAM except shown in Figure 51 and 52 are
undefined, so set the initial value to them.
Fig 51. Internal state at reset (1)
0
Program counter (PC)
Address 0 in page 0 is set to program counter.
Interrupt enable flag (INTE)
Power down flag (P)
External 0 interrupt request flag (EXF0)
Interrupt control register V1
Interrupt control register V2
Interrupt control register I1
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Timer 3 interrupt request flag (T3F)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
Timer control register PA
Timer control register W1
Timer control register W2
Timer control register W3
Timer control register W4
Clock control register MR
Clock control register RG
LCD control register L1
LCD control register L2
LCD control register L3
LCD control register C1
LCD control register C2
LCD control register C3
0
(Interrupt disabled)
0
(Interrupt disabled)
0
(Interrupt disabled)
0
1
0
(Prescaler stopped)
0
(Timer 1 stopped)
0
(Timer 2 stopped)
0
1
0
(Timer 3 stopped)
(Timer LC stopped)
0
1
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