參數(shù)資料
型號(hào)： M34524EDFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁(yè)數(shù)： 28/66頁(yè)
文件大?。?/td> 1936K
代理商： M34524EDFP
Rev.1.04
Aug 23, 2007
Page 34 of 146
REJ03B0188-0104
4559 Group
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. This function is valid only when the timer 1 control start synchronous circuit is selected (I10 =“1”).
Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source.
Table 17 Timer control registers
Timer control register PA
at reset : 02
at power down : 02
W
TPAA
PA0
Prescaler control bit
0
Stop (state retained)
1Operating
Timer control register W1
at reset : 00002
at power down : state retained
R/W
TAW1/TW1A
W13
Timer 1 count auto-stop circuit selection bit
(Note 2)
0
Timer 1 count auto-stop circuit not selected
1
Timer 1 count auto-stop circuit selected
W12 Timer 1 control bit
0
Stop (state retained)
1Operating
Timer 1 count source selection bits (Note 3)
W11 W10
Count source
W11
0
PWM signal (PWMOUT)
0
1
Prescaler output (ORCLK)
1
0
Timer 3 underflow signal (T3UDF)
W10
1
CNTR input
Timer control register W2
at reset : 00002
at power down : 00002
R/W
TAW2/TW2A
W23 CNTR pin function control bit
0
CNTR pin output invalid
1
CNTR pin output valid
W22
PWM signal
“H” interval expansion function control bit
0
PWM signal “H” interval expansion function invalid
1
PWM signal “H” interval expansion function valid
W21 Timer 2 control bit
0
Stop (state retained)
1Operating
W20 Timer 2 count source selection bit
0XIN input
1
Prescaler output (ORCLK)/2
Timer control register W3
at reset : 00002
at power down : state retained
R/W
TAW3/TW3A
W33 Timer 3 count source selection bit
0XCIN input
1
Prescaler output (ORCLK)
W32 Timer 3 control bit
0
Stop (initial state)
1Operating
Timer 3 count value selection bits
W31 W30
Count value
W31
0
Underflow every 8192 count
0
1
Underflow every 16384 count
1
0
Underflow every 32768 count
W30
1
Underflow every 65536 count
Timer control register W4
at reset : 00002
at power down : state retained
R/W
TAW4/TW4A
W43 Timer LC control bit
0
Stop (state retained)
1Operating
W42 Timer LC count source selection bit
0Bit 4 (T34) of timer 3
1
System clock (STCK)
W41
CNTR pin output auto-control circuit
selection bit
0
CNTR output auto-control circuit not selected
1
CNTR output auto-control circuit selected
W40 CNTR pin input count edge selection bit
0
Falling edge
1
Rising edge
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