- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359054 > M30LW128D110ZE1T (意法半導(dǎo)體) 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product PDF資料下載
參數(shù)資料
| 型號： | M30LW128D110ZE1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
| 中文描述： | 128兆位（兩個64兆比特，x8/x16，統(tǒng)一座，快閃記憶體）3V電源，多記憶體產(chǎn)品 |
| 文件頁數(shù)： | 15/57頁 |
| 文件大小： | 860K |
| 代理商： | M30LW128D110ZE1T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
15/57
M30LW128D
BUS OPERATIONS
There are 6 bus operations that control each mem-
ory. Each of these is described in this section, see
Tables 4, Bus Operations, for a summary.
On Power-up or after a Hardware Reset the device
defaults to Read Array mode (Page Read).
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the device and do
not affect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers (Electronic Sig-
nature, Status Register, CFI and Block Protection
Status) in the Command Interface.
A valid bus operation involves setting the desired
address on the Address inputs, enabling the de-
vice (refer to Table 3), applying a Low signal, V
IL
,
to Output Enable and keeping Write Enable High,
V
IH
.
The Data Inputs/Outputs will output the value, see
Figure 11, Bus Read AC Waveforms, and Table
16, Bus Read AC Characteristics, for details of
when the output becomes valid.
Page Read.
Page Read operations are used to
read from several addresses within the same
memory page.
Each memory page is a 4 Words or 8 Bytes and
has the same A3-A22. In x8 mode only A0, A1 and
A2 may change, in x16 mode only A1 and A2 may
change.
Valid bus operations are the same as Bus Read
operations but with different timings. The first read
operation within the page has identical timings,
subsequent reads within the same page have
much shorter access times. If the page changes
then the normal, longer timings apply again. See
Figure 12, Page Read AC Waveforms and Table
17, Page Read AC Characteristics for details on
when the outputs become valid.
Bus Write.
Bus Write operations write to the
Command Interface in order to send commands to
the device or to latch addresses and input data to
program.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts and enabling the device (refer to Chip Enable
section).
Both the Address Inputs and Data Input/Outputs
are latched by the Command Interface on the ris-
ing edge of Write Enable or Chip Enable, whichev-
er occurs first.
Output Enable must remain High, V
IH
, during the
whole Bus Write operation. See Figures 13, and
14, Write AC Waveforms, and Tables 18 and 19,
Write and Chip Enable Controlled Write AC Char-
acteristics, for details of the timing requirements.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Standby.
When Chip Enable is High, V
IH
, the de-
vice enters Standby mode and the Data Inputs/
Outputs pins are placed in the high impedance
state regardless of Output Enable or Write Enable.
The Supply Current is reduced to the Standby
Supply Current, I
DD1
.
During Program or Erase operations the device
will continue to use the Program/Erase Supply
Current, I
DD3
, for Program or Erase operations un-
til the operation completes.
Automatic Low Power.
If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the device
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Supply Current, I
DD5
. The Data Inputs/Outputs will
still output data if a Bus Read operation is in
progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Power-Down.
The device is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
DD2
, and the outputs are high impedance,
independent of Chip Enable, Output Enable or
Write Enable.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30LW128D110ZE6T | 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
| M34559G6 | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G4 | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M3488Q1 | 256 x 256 DIGITAL SWITCHING MATRIX |
| M3488 | 256 x 256 DIGITAL SWITCHING MATRIX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30LW128D110ZE6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
| M30MC003 | 制造商:BLACK BOX 功能描述:COLLAR |
| M30MHWS | 制造商:OMRON AUTOMATION AND SAFETY 功能描述:MOUNTING HARDWARE FOR M30 SENSOR 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:Mounting Hardware For M18 Size Sensors |
| M30-MHWS | 功能描述:繼電器插座與硬件 2 NUTS,1 WASHER WASHER, M30 DIA. RoHS:否 制造商:TE Connectivity / Schrack 附件類型:Socket 相關(guān)繼電器系列:RP, RT, RY 端接類型:PCB 極數(shù):1 |
| M30PHWS | 制造商:OMRON AUTOMATION AND SAFETY 功能描述:MOUNT HARDWARE 2PLASTIC NUTS M30 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:NUT SET FOR E2F |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。