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參數(shù)資料
| 型號： | M30LW128D110ZE1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product |
| 中文描述： | 128兆位（兩個64兆比特，x8/x16，統(tǒng)一座，快閃記憶體）3V電源，多記憶體產(chǎn)品 |
| 文件頁數(shù)： | 11/57頁 |
| 文件大小： | 860K |
| 代理商： | M30LW128D110ZE1T |
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M30LW128D
I
Status - the pin gives a pulsing signal to indicate
the end of a Program or Block Erase operation.
After power-up or reset the STS pin is configured
in Ready/Busy mode. The pin can be configured
for Status mode using the Configure STS com-
mand.
When the Program/Erase Controller is idle, or sus-
pended, STS can float High through a pull-up re-
sistor. The use of an open-drain output allows the
STS pins from several devices to be connected to
a single pull-up resistor (a Low will indicate that
one, or more, of the memories is busy).
STS is not Low during a reset unless the reset was
applied when the Program/Erase controller was
active.
The STS signal is not available with the LFBGA88
package.
Program/Erase Enable (V
PEN
).
The
Erase Enable input, V
PEN,
is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
Program/
wise the operations is not guaranteed to succeed
and data may become corrupt.
V
DD
Supply Voltage.
V
DD
provides the power
supply to the internal core of the device. It is the
main power supply for all operations (Read, Pro-
gram and Erase).
V
DDQ
Supply Voltage.
V
DDQ
provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from V
DD
. V
DDQ
can be
tied to V
DD
or can use a separate supply.
It is recommended to power-up and power-down
V
DD
and V
DDQ
together to avoid any condition that
would result in data corruption.
V
SS
Ground.
Ground, V
SS,
is the reference for
the core power supply. It must be connected to the
system ground.
V
SSQ
Ground.
V
SSQ
ground is the reference for
the input/output circuitry driven by V
DDQ
. V
SSQ
must be connected to V
SS
.
Note: Each device in a system should have
V
DD
and
V
DDQ
decoupled with a 0.1μF ceramic
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 10, AC Measurement Load Circuit.
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