參數(shù)資料
型號: M30L0R7000T0ZAQF
廠商: 意法半導(dǎo)體
英文描述: CAP 0.1UF 50V 10% X7R DIP-2 BULK R-MIL-C-39014
中文描述: 128兆位(8兆x16插槽,多銀行,多層次,多突發(fā)),1.8V電源快閃記憶體
文件頁數(shù): 46/83頁
文件大?。?/td> 1329K
代理商: M30L0R7000T0ZAQF
M30L0R7000T0, M30L0R7000B0
46/83
Figure 15. Clock input AC Waveform
Table 22. Synchronous Read AC Characteristics
Note: 1. Sampled only, not 100% tested.
2. For other timings please refer to
Table 21., Asynchronous Read AC Characteristics
.
Symbol
Alt
Parameter
M30L0R7000T0/B0
Unit
85
S
t
AVKH
t
AVCLKH
Address Valid to Clock High
Min
7
ns
t
ELKH
t
ELCLKH
Chip Enable Low to Clock High
Min
7
ns
t
ELTV
Chip Enable Low to Wait Valid
Max
14
ns
t
EHEL
Chip Enable Pulse Width (subsequent
synchronous reads)
Min
14
ns
t
EHTZ
Chip Enable High to Wait Hi-Z
Max
17
ns
t
KHAX
t
CLKHAX
Clock High to Address Transition
Min
7
ns
t
KHQV
t
KHTV
t
CLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
14
ns
t
KHQX
t
KHTX
t
CLKHQX
Clock High to Output Transition
Clock High to WAIT Transition
Min
3
ns
t
LLKH
t
ADVLCLKH
Latch Enable Low to Clock High
Min
7
ns
C
t
KHKH
t
CLK
Clock Period (f=40MHz)
Min
ns
Clock Period (f=47MHz)
Min
Clock Period (f=54MHz)
Min
18.5
ns
t
KHKL
t
KLKH
Clock High to Clock Low
Clock Low to Clock High
Min
3.5
ns
t
f
t
r
Clock Fall or Rise Time
Max
3
ns
AI06981
tKHKH
tf
tr
tKHKL
tKLKH
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M30L0R7000T0ZAQT CAP 0.22UF 50V 20% X7R DIP-2 BULK R-MIL-C-39014
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參數(shù)描述
M30L0R7000T0ZAQT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
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M30L0R8000B0 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQ 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQE 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory