參數(shù)資料
型號(hào)： M30L0R7000T0ZAQF
廠(chǎng)商： 意法半導(dǎo)體
英文描述： CAP 0.1UF 50V 10% X7R DIP-2 BULK R-MIL-C-39014
中文描述： 128兆位（8兆x16插槽，多銀行，多層次，多突發(fā)），1.8V電源快閃記憶體
文件頁(yè)數(shù)： 25/83頁(yè)
文件大小： 1329K
代理商： M30L0R7000T0ZAQF
25/83
M30L0R7000T0, M30L0R7000B0
CONFIGURATION REGISTER
The Configuration Register is used to configure
the type of bus access that the memory will per-
form. Refer to Read Modes section for details on
read operations.
The Configuration Register is set through the
Command Interface using the Set Configuration
Register command. After a reset or power-up the
device is configured for asynchronous read (CR15
= 1). The Configuration Register bits are described
in
Table 10.
They specify the selection of the burst
length, burst type, burst X latency and the read op-
eration. Refer to Figures
6
and
7
for examples of
synchronous burst configurations.
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch be-
tween Asynchronous and Synchronous Read op-
erations.
When the Read Select bit is set to ’1’, read opera-
tions are asynchronous; when the Read Select bit
is set to ’0’, read operations are synchronous.
Synchronous Burst Read is supported in both pa-
rameter and main blocks and can be performed
across banks.
On reset or power-up the Read Select bit is set to
’1’ for asynchronous access (default).
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available.
For correct operation the X-Latency bits can only
assume the values in
Table 10., Configuration
Register
.
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system pa-
rameters. Two conditions must be satisfied:
1.
Depending on whether t
AVK_CPU
or t
DELAY
is
supplied either one of the following two
equations must be satisfied:
(n + 1) t
K
≥
t
AVQV
- t
AVK_CPU
+ t
QVK_CPU
(n + 2) t
K
≥
t
AVQV
+ t
DELAY
+ t
QVK_CPU
2.
and also
t
K
> t
KQV
+ t
QVK_CPU
where
n is the chosen X-Latency configuration code
t
K
is the clock period
t
AVK_CPU
is clock to address valid, L Low, or E
Low, whichever occurs last
t
DELAY
is address valid, L Low, or E Low to
clock, whichever occurs last
■
■
■
■
■
t
QVK_CPU
is the data setup time required by
the system CPU,
t
KQV
is the clock to data valid time
t
AVQV
is the random access time of the device.
Refer to
Figure 6., X-Latency and Data Output
Configuration Example
.
Wait Polarity Bit (CR10)
The Wait Polarity bit is used to set the polarity of
the Wait signal used in Synchronous Burst Read
mode. During Synchronous Burst Read mode the
Wait signal indicates whether the data output are
valid or a WAIT state must be inserted.
When the Wait Polarity bit is set to ‘0’ the Wait sig-
nal is active Low. When the Wait Polarity bit is set
to ‘1’ the Wait signal is active High (default).
Data Output Configuration Bit (CR9)
The Data Output Configuration bit is used to con-
figure the output to remain valid for either one or
two clock cycles during synchronous mode.
When the Data Output Configuration Bit is ’0’ the
output data is valid for one clock cycle, when the
Data Output Configuration Bit is ’1’ the output data
is valid for two clock cycles.
The Data Output Configuration must be config-
ured using the following condition:
t
K
> t
KQV
+ t
QVK_CPU
where
t
K
is the clock period
t
QVK_CPU
is the data setup time required by
the system CPU
t
KQV
is the clock to data valid time.
If this condition is not satisfied, the Data Output
Configuration bit should be set to ‘1’ (two clock cy-
cles). Refer to
Figure 6., X-Latency and Data Out-
put Configuration Example
.
Wait Configuration Bit (CR8)
The Wait Configuration bit is used to control the
timing of the Wait output pin, WAIT, in Synchro-
nous Burst Read mode.
When WAIT is asserted, Data is Not Valid and
when WAIT is de-asserted, Data is Valid.
When the Wait Configuration bit is Low (set to ’0’)
the Wait output pin is asserted during the wait
state. When the Wait Configuration bit is High (set
to ’1’) (default) the Wait output pin is asserted one
clock cycle before the wait state.
Burst Type Bit (CR7)
The Burst Type bit determines the sequence of ad-
dresses read during Synchronous Burst Reads.
The Burst Type bit is High (set to ’1’), as the mem-
ory outputs from sequential addresses only.
■
■
■
■
■
■
相關(guān)PDF資料
PDF描述
M30L0R7000T0ZAQT CAP 0.22UF 50V 20% X7R DIP-2 BULK R-MIL-C-39014
M30L0R7000B0ZAQT CAP 0.047UF 100V 20% X7R DIP-2 BULK R-MIL-C-39014
M30L0R8000T0ZAQ 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0ZAQF 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000T0ZAQT 256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30L0R7000T0ZAQT 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
M30L0R7000XX 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
M30L0R8000B0 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQ 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
M30L0R8000B0ZAQE 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory
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