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| 型號： | M30828MH-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 35/48頁 |
| 文件大?。?/td> | 847K |
| 代理商： | M30828MH-XXXGP |
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fective jitter added by the ADC is beyond user control, the best
the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
Input clock amplitudes above those specified in the Converter
Electrical Characteristics may result in increased input offset
voltage. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
2.5 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the AD-
C08D1520 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Self Calibration, Output Edge
Synchronization choice, LVDS Output Level choice and a
Power Down feature.
2.5.1 Full-Scale Input Range Setting
The input full-scale range can be selected with the FSR con-
trol input (pin 14) in the Normal Mode of operation. The input
full-scale range is specified as V
IN in the Converter Electrical
Characteristics. In the Extended Control Mode, the input full-
scale range may be programmed using the Full-Scale Adjust
Voltage register. See 2.3 THE ANALOG INPUT for more in-
formation.
2.5.2 Calibration
The ADC08D1520 calibration must be run to achieve speci-
fied performance. The calibration must be initiated by the
user. The calibration procedure is exactly the same whether
there is an input clock present upon power up or if the clock
begins some time after application of power. The CalRun out-
put indicator is high while a calibration is in progress. Note
that the DCLK outputs are not active during a calibration cycle
by default, therefore it is not recommended for use as a sys-
tem clock. The DCLK outputs are continuously present at the
output only when the Resistor Trim Disable is activated.
2.5.2.1 Initiating Calibration
A calibration may be run at any time in both the Non-DES and
DES Modes. After power-up, we recommend that the part be
calibrated with the Resistor Trim Disable inactive once the
power supplies have stabilized and the temperature of the
chip has stabilized. When a calibration is run with the Resistor
Trim Disable inactive, both the ADC and the input termination
resistor are calibrated. However, since the input termination
resistance changes only marginally with temperature, the us-
er has the option to disable the input termination resistor
calibration for subsequent calibrations, which will guarantee
that the DCLK is continuously present at the output. The Re-
sistor Trim Disable can be programmed in the Extended
Configuration register (Addr: 9h) when in the Extended Con-
trol Mode. Refer to Extended Configuration Register for reg-
ister programming information.
As dynamic performance changes slightly with junction tem-
perature, a calibration may be executed to bring the perfor-
mance of the ADC in line. Two methods can be used initiate
a calibration. The first method is to hold the CAL pin low for
at least t
CAL_L input clock cycles, then hold it high for at least
another t
CAL_H input clock cycles. The second method is to
program the CAL bit in the Calibration register while in Ex-
tended Control Mode. The functionality of the CAL bit is
exactly the same as using the CAL pin. The CAL bit must be
programmed to 0b for a minimum of t
CAL_Linput clock cycles
and then programmed to 1b for a minimum of t
CAL_H input
clock cycles to initiate a calibration cycle. The CalRun signal
should be monitored to determine when the calibration cycle
has completed. The CalRun pin will become a logic high in-
dicating an active calibration cycle regardless of which
method was used to initiate the calibration cycle. Note that the
DCLK outputs are not active during a calibration cycle; there-
fore, it is not recommended for use as a system clock.
The minimum number of t
CAL_L and tCAL_H input clock cycle
sequences are required to ensure that random noise does not
cause a calibration to begin when it is not desired. As men-
tioned in 1.1 OVERVIEW, for best performance, a calibration
should be performed 20 seconds or more after power up and
repeated when the operating temperature changes signifi-
cantly relative to the specific system design performance
requirements. Dynamic performance changes slightly with in-
creasing junction temperature and can be easily corrected by
performing a calibration.
2.5.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that DCLK signal can be used to latch the output data
into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
At the very high speeds of which the ADC08D1520 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
2.5.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
For short LVDS lines and low noise systems, satisfactory per-
formance may be realized with the OutV input low. If the LVDS
lines are long and/or the system in which the ADC08D1520
is used is noisy, it may be necessary to tie the OutV pin high.
2.5.5 Dual Edge Sampling
The Dual Edge Sampling (DES) feature causes one of the two
input pairs to be routed to both ADCs. The other input pair is
deactivated. One of the ADCs samples the input signal on the
rising input clock edge (duty cycle corrected), the other sam-
ples the input signal on the falling input clock edge (duty cycle
corrected). If the device is in the 1:4 Demux DES Mode, the
result is an output data rate 1/4 that of the interleaved sample
rate which is twice the input clock frequency. Data is present-
ed in parallel on all four output buses in the following order:
DQd, DId, DQ, DI. If the device is the Non-Demultiplex output
mode, the result is an output data rate 1/2 that of the inter-
leaved sample rate. Data is presented in parallel on two
output buses in the following order: DQ, DI.
To use this feature in the Non-Extended Control Mode, tie pin
127 to V
A/2 and the signal at the I- channel input will be sam-
pled by both converters.
In the Extended Control Mode, either input may be used for
dual edge sampling. See 1.1.5.1 Dual-Edge Sampling.
www.national.com
40
ADC08D1520QML
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