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參數資料
| 型號： | M30828MH-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, MROM, 30 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數： | 21/48頁 |
| 文件大小： | 847K |
| 代理商： | M30828MH-XXXGP |
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1.0 Functional Description
The ADC08D1520 is a versatile A/D Converter with an inno-
vative architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is not recommended in radiation environments to al-
low an active pin to float, pins 4, 14, 52 and 127 of the
ADC08D1520 are designed to be left floating without jeopardy
in non radiation environments. In all discussions throughout
this data sheet, whenever a function is called by allowing a
control pin to float, connecting that pin to a potential of one
half the V
A supply voltage is recommended for radiation en-
vironments.
1.1 OVERVIEW
The ADC08D1520 uses a calibrated folding and interpolating
architecture that achieves over 7.25 effective bits. The use of
folding amplifiers greatly reduces the number of comparators
and power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 200 MSPS
to 1.7 GSPS, typical. Differential input voltages below nega-
tive full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at either the I- or Q- Channel input will cause
the OR (Out of Range) output to be activated. This single OR
output indicates when the output code from one or both of the
channels is below negative full scale or above positive full
scale.
Each converter has a selectable output demultiplexer which
feeds two LVDS buses. If the 1:2 Demultiplexed Mode is se-
lected, the output data rate is reduced to half the input sample
rate on each bus. When Non-Demultiplexed Mode is select-
ed, that output data rate on channels DI and DQ are at the
same rate as the input sample clock.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erro-
neous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
1.1.1 Calibration
The ADC08D1520 has a calibration feature which must be
invoked by the user. If the device is powered-up in the Ex-
tended Control Mode, the registers will be in an unknown state
and no calibration is performed. For the initial calibration after
power-up, we recommend that the registers first be pro-
grammed to a known state before performing a calibration or
the part be calibrated in the pin control mode. All subsequent
calibrations can be run in either the Non-Extended Control
Mode or the Extended Control Mode.
The calibration algorithm consists of two portions. The first
portion is calibrating the analog input. This calibration trims
the 100
analog input differential termination resistor and
minimizes full-scale error, offset error, DNL and INL, resulting
in maximizing SNR, THD, SINAD (SNDR) and ENOB. This
portion of the calibration can be disabled by programming the
Resistor Trim Disable (RTD) bit in the Extended Configuration
register in the Extended Control Mode. Disabling the input
termination resistor is not recommended for the initial cali-
bration after power-up. The second portion of the calibration
cycle is the ADC calibration in which internal bias currents are
set. The ADC calibration is performed regardless of the RTD
bit setting. Running the calibration is an important part of this
chip’s functionality and is required in order to obtain specified
performance. In addition to the requirement that a calibration
be run at power-up, a calibration must be run whenever the
FSR pin is changed. For best performance, we recommend
that a calibration be run after application of power once the
power supplies have settled and the part temperature has
stabilized. Further calibrations should be run whenever the
operating temperature changes significantly relative to the
specific system performance requirements. See 2.5.2.1 Initi-
ating Calibration for more information. Calibration can not be
initiated or run while the device is in the Power-Down Mode.
See1.1.7 Power Down for information on the interaction be-
tween Power down and calibration.
In normal operation, calibration should be performed just after
application of power and whenever a valid calibration com-
mand is given. A calibration command can be issued using
two methods. The first method is to hold the CAL pin low for
at least t
CAL_L input clock cycles, then hold it high for at least
another t
CAL_H input clock cycles as defined in the Converter
Electrical Characteristics. The second method is to program
the CAL bit in the Calibration register. The functionality of the
CAL bit is exactly the same as using the CAL pin. The CAL
bit must be programmed to 0b for t
CAL_L input clock cycles and
then programmed to 1b for at least t
CAL_H input clock cycles
to initiate a calibration cycle. The time taken by the calibration
procedure is specified as t
CAL in the Converter Electrical
Characteristics.
The CAL bit does not reset itself to zero automatically, but
must be manually reset before another calibration event is
desired, the CAL bit may be left high indefinitely, with no neg-
ative consequences.
The RTD bit setting is critical for running a calibration event
with the Clock Phase Adjust enabled. If initiating a calibration
event while the Clock Phase Adjust is enabled, the RTD bit
must be set to high, or no calibration will occur. If initiating a
calibration event while the Clock Phase Adjust is not enabled,
a normal calibration will occur, regardless of the setting of the
RTD bit.
Calibration Operation Notes:
During the calibration cycle, the OR output may be active
as a result of the calibration algorithm. All data on the
output pins and the OR output are invalid during the
calibration cycle.
During the calibration, all clocks are halted on chip,
including internal clocks and DCLK, while the input
termination resistor is trimmed to a value that is equal to
R
EXT / 33. This is to reduce noise during the input resistor
calibration portion of the calibration cycle. See for
information on maintaining DCLK operation during on-
command calibration.
This external resistor is located between pin 32 and
ground. R
EXT must be 3300 ±0.1%. With this value, the
input termination resistor is trimmed to be 100
. Because
R
EXT is also used to set the proper current for the Track
and Hold amplifier, for the preamplifiers and for the
comparators, other values of R
EXT should not be used.
The CalRun output is high whenever the calibration
procedure is running. This is true whether the calibration
is done at power-up or on-command.
www.national.com
28
ADC08D1520QML
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