deveopmen
Clock synchronous serial I/O mode
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
139
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the port function select register (bits of related to-P6
4
and P6
5
). (See Figure 1.17.5.)
The multiple pins function is valid only when the internal clock is selected for UART1. Note that when
this function is selected, UART1 CTS/RTS function cannot be used.
Figure 1.17.5. The transfer clock output from the multiple pins function usage
Microcomputer
T
X
D
1
(P6
7
)
CLKS
1
(P6
4
)
CLK
1
(P6
5
)
IN
CLK
IN
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 0370
16
, bit 5 at address 033D
16
,
032D
16
, 02FD
16
) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the
receive buffer register is read out, the unit simultaneously goes to a receive enable state without
having to set dummy data to the transmit buffer register back again.
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
(f) Serial data logic switch function (UART2 to UART4)
When the data logic select bit (bit6 at address 033D
16
, 032D
16
, 02FD
16
) = “1”, and writing to transmit
buffer register or reading from receive buffer register, data is reversed. Figure 1.17.6 shows the
example of serial data logic switch timing.
Figure 1.17.6. Serial data logic switch timing
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Transfer clock
TxD
i
(no reverse)
TxD
i
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
When LSB first