
Clock-Synchronous Serial I/O
M30240 Group
Rev.1.00 Sep 24, 2003 Page 186 of 360
2.4.2 Operation
2.4.2.1 Transmission in clock-synchronous serial I/O mode
In transmitting data in clock-synchronous serial I/O mode, select functions from those listed in Table
2.14. An example using the indicated options is described below. Figure 2.46 shows the operation
timing, and Figures 2.47 and 2.48 show the set-up procedures.
Table 2.14:
Serial I/O transmission in clock synchronous serial I/O mode functions
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
selected, the CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disabled bit to “0”.
Note 2: UART2 only.
Operation
(1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit butter reg-
ister makes data transmission status ready.
(2) When the input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be con-
trolled on the reception side).
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the UARTi
transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is transmitted from
the TxDi pin. Then the data is transmitted bit by bit from the lower order in synchronization with the
falling edges.
(4) When transmission of 1-byte of data is completed, the transmit register empty flag goes to “1”,
which indicates that transmission is completed. The transfer clock stops at “H” level.
(5) If the next transmission data is set in the UARTi transmit buffer register while a transmission is in
progress (before the eighth bit has been transmitted), the data is transmitted in succession.
Item
Set-up
Item
Set-up
Transfer clock source
O
Internal clock (f1/f8/f32)
Transmission interrupt
factor
O
Transmission buffer empty
External clock (CLKi pin)
Transmission complete
CTS function
O
CTS function enabled
Output transfer clock to
multiple pins (Note 1)
O
Not selected
CTS function disabled
Selected
CLK polarity
O
Output transmission data at the
falling edge of the transfer clock
Data logic select function
(Note 2)
O
No reverse
Output transmission data at the
rising edge of the transfer clock
Reverse
Transfer clock
O
LSB first
TxD, RxD I/O polarity
reverse bit (Note 2)
O
No reverse
MSB first
Reverse