
1-114
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
Clock Synchronous Serial I/O Mode
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ClockSynchronousSerial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.34
and 1.35 list the specifications of the clock synchronous serial I/O mode. Figure 1.87 shows the UARTi
transmit/receive mode register.
Table 1.34. Specifications of clock synchrounous serial I/O mode (1)
Note 1: n denotes the value 00 16 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in.
Also, the UART receive interrupt requst bit is not set to 1 .
Item
Specification
Transfer data format
Transfer data length: 8 bits
Transfer clock
When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = 0 ): fi/
2 (n+1) (Note 1) fi = f1, f8, f32
When external clock is selected (bit 3 at addresses 03A016, 03A816 037816 = 1 ):
Input from CLKi pin
Transmission/
reception control
CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start
condition
To start transmission, the following requirements must be met:
-Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = 1
-Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = 0
-When CTS function selected, CTS input level = L
If external clock is selected, the following requirements must also me be:
-CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16,) = 0 : CLKi
input level = H
-CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = 1 : CLKi
input level = L
Receiving start
condition
To start reception, the following requirement must be met:
-Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = 1
-Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = 1
-Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = 0
If external clock is selected, the following requirements must also be met:
-CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = 0 : CLKi
input level = H
-CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = 1 : CLKi
input level = L
Interrupt request
generation timing
When transmitting:
-Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address
037D16) = 0 : Interrupts requested when data transferred from UARTi transfer buffer
register to UARTi transmit register is complete
-Transmit interrupt cause select bit (bit 0, 1 at address 03B016, bit 4 at address
037D16) = 1 : Interrupts requested when data transmission from UARTi transfer reg-
ister is complete
When receiving:
-Interrupts requested when data transferred from UARTi receive register to UARTi
receive buffer register is complete.
Error detection
Overrun error (Note 2)
This error occurs when the next data are ready before contents of UARTi receive
buffer register are read out