
1-25
Under
development
Specifications in this manual are tentative and subject to change
Rev. H
Clock Generating Circuit
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 1.14. Clock control registers 0 and 1
System clock control register 0 (Note 1)
Symbol
Address
When reset
CM0
000616
4816
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
0 0 : I/O port P75
0 1 : fC1 output
1 0 : f1 output
1 1 : Clock divide counter output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bits
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 7)
Xcin-Xout
drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
0 : I/O port
1 : Xcin - Xcout generation
Main clock (Xin -Xout )
stop bit (Note 3, 4)
0 : Main clock on
1 : Main clock off
Main clock division select
bit 0 (Note 6)
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 5)
0 : Xin, Xout
Xcin, Xcout
1 :
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: Changes to "1" when shifting to stop mode and at a reset.
Note 3: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 4: If this bit is set to "1", Xout turns "H". The built-in feedback resistor remains being connected, so X IN turns
pulled up to Xout ("H") via the feedback resistor.
Note 5: Set subclock (Xcin - Xcout) enable bit (CM04) to "1" and allow the subclock to stabilize before setting CM07 from
from "0" to "1". Do not write to both bits at the same time. Likewise, set the main clock stop bit (CM05) to "0" and
allow the subclock to stabilize before settng CM07 bit from "1" to "0".
Note 6: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 7: fC, fC132, fC1, fC32 is not included.
System clock control register 1 (Note 1)
Symbol
Address
When reset
CM1
000716
2016
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
CM10
All clock stop control bit
(Note 4)
0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is
fixed at 8.
Note 4: If this bit is set to "1", Xout goes "H", and the built-in feedback resistor is cut off. Xcin and Xcout goes into high
CM15
Xin -Xout drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
W
R
W
R
CM16
CM17
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
0
Reserved bit
Always set to
"0"
0
CM14
fC132 clock select bit
0 : fC32
1 : fC1
Port Xc Select Bit
impedance state.