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Under
development
Specifications in this manual are tentative and subject to change
Rev. H
Serial I/O Mode 1 (Flash Memory Version)
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard serial I/O mode 1 (clock synchronous)
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed
to operate (read, program erase, etc.) the internal flash memory. There are two standard serial I/O
modes that require a purpose specific peripheral unit.
Serial I/O Mode 1 is synchronized
Serial I/O Mode 2 is as asynchronized
The standard serial I/O mode is different from the parallel I/O mode because it uses the CPU rewrite
mode commands to control flash memory operations. It is started when it comese out of reset with the
P50 (CE) pin set “High", the P55 (EPM) pin set "Low" and the CNVss pin set "High". In an ordinary
command mode, the CNVss pin is set to "Low".
This control program is written in the boot ROM area when the product is shipped from Mitsubishi.
Please note that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in
parallel I/O mode. In standard serial I/O mode, only the user ROM area (see Figure 1.181) can be
rewritten. The boot ROM cannot.
Also, for security, a 7-byte ID code is used. When there is data in the flash memory, most commands
sent from the peripheral unit are not accepted unless the ID code matches.
Figure 1.161 shows the pin connections for the standard serial I/O mode. Serial data I/O uses UART0
and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 and mode 2
according to the level of CLK0 pin when the reset is released.
Serial I/O Mode 1
Serial I/O mode 1 uses a synchronous communications protocol and is selected by holding the CLK0 pin
"Low" out of reset. The operation uses the four UART0 pins CLK0, RxD0, TxD0 and RTS0 (BUSY). the CLK0
pin is the transfer clock input pin through which an external transfer clock is input. The TxD0 pin is for CMOS
output. the RTS0 (BUSY) pin outputs an “L” level when ready for reception and “H” level when reception starts.
Serial I/O Mode 2
To use standard serial I/O mode 2, set the CLK0 pin to “L” before coming out of reset. The operation uses the
two UART0 pins RxD0 and TxD0.
Overview of standard serial I/O mode 1
In standard serial I/O mode 1, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programmer) using 4-wire clock-synchronous serial I/O (UART0). Standard
serial I/O mode 1 is engaged by coming out of reset with the P56 (CLK0) pin “H” level.
In reception, software commands, addresses and program data are synchronized with the rise of the transfer
clock that is input to the CLK0 pin, and are then input to the MCU via the RxD0 pin. In transmission, the read
data and status are synchronized with the fall of the transfer clock, and output from the TxD0 pin. The TxD0 pin
is for CMOS output. Transfer is in 8-bit units LSB first.
When busy, such as during transmission, reception, erasing or program execution the RTS0 (BUSY) pin is “H”
level. Accordingly, always start the next transfer after the RTS0 (BUSY) pin is “L” level.
Also, data and status register in memory can be read after inputting software commands. Status, such as the
operating state of the flash memory or whether a program or erase operation ended successfully or not, can
be checked by reading the status register.