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參數(shù)資料
| 型號： | M2Y51264TU88A2G-37B |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 444K |
| 代理商： | M2Y51264TU88A2G-37B |
M2Y51264TU88A2G/ M2Y1G64TU8HA2G
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.0
15
6/2006
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
-37B
-3C
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
Notes
tAC
DQ output access time from CK/
-0.5
+0.5
-0.45 +0.45
ns
tDQSCK
DQS output access time from CK/
-0.45
+0.45
-0.4
+0.4
ns
tCH
CK high-level width
0.45
0.55
0.45
0.55
tCK
tCL
CK low-level width
0.45
0.55
0.45
0.55
tCK
tHP
Minimum half clk period for any given cycle; defined
by clk high (tCH) or clk low (tCL) time
tCH
or
tCL
-
tCH
or
tCL
-
tCK
tCK
Clock Cycle Time
3.75
8
3
8
ns
tDH
DQ and DM input hold time
225
-
175
-
ps
tDS
DQ and DM input setup time
100
-
100
-
ps
tIPW
Input pulse width
0.6
-
0.6
-
tCK
tDIPW
DQ and DM input pulse width (each input)
0.35
-
0.35
-
tCK
tHZ
Data-out high-impedance time from CK/
-
tAC max
-
tAC max
ns
tLZ(DQ)
Data-out low-impedance time from CK/
2tAC min tAC max 2tAC min tAC max
ns
tLZ(DQS) DQS low-impedance time from CK/
tAC min
tAC max tAC min tAC max
ns
tDQSQ
DQS-DQ skew (DQS & associated DQ signals)
-
0.30
-
0.24
ns
tQHS
Data hold Skew Factor
-
0.4
-
0.34
ns
tQH
Data output hold time from DQS
tHP -
tQHS
-
tHP -
tQHS
-
ns
tDQSS
Write command to 1st DQS latching transition
-0.25
0.25
-0.25
0.25
tCK
tDQSH
DQS input high pulse width
0.35
-
0.35
-
tCK
tDQSL
DQS input low pulse width
0.35
-
0.35
-
tCK
tDSS
DQS falling edge to CK setup time
(write cycle)
0.2
-
0.2
-
tCK
tDSH
DQS falling edge hold time from CK
(write cycle)
0.2
-
0.2
-
tCK
tMRD
Mode register set command cycle time
2
-
2
-
tCK
tWPST
Write postamble
0.40
0.60
0.40
0.60
tCK
tWPRE
Write preamble
0.35
-
0.35
-
tCK
tIH
Address and control input hold time
0.375
-
0.275
-
ns
tIS
Address and control input setup time
0.25
-
0.2
-
ns
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tCK
tRPST
Read postamble
0.4
0.6
0.4
0.6
tCK
tDelay
Minimum time clocks remains ON after CKE
asynchronously drops Low
tIS + tCK
+ tIH
-
tIS +
tCK +
tIH
-
ns
tRFC
Refresh to active/Refresh command time
105
ns
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