- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296349 > M2Y51264TU88A2G-37B (NANYA TECHNOLOGY CORP) 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 PDF資料下載
參數(shù)資料
| 型號： | M2Y51264TU88A2G-37B |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 444K |
| 代理商： | M2Y51264TU88A2G-37B |
M2Y51264TU88A2G/ M2Y1G64TU8HA2G
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.0
4
6/2006
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK1, CK2
(SSTL)
Positive
Edge
The positive line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the
rising edge of their associated clocks.
,
(SSTL)
Negative
Edge
The negative line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL.
CKE0, CKE1
(SSTL)
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
,
(SSTL)
Active
Low
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
,
(SSTL)
Active
Low
When sampled at the positive rising edge of the clock,
,
define the
operation to be executed by the SDRAM.
VREF
Supply
Reference voltage for SSTL-18 inputs
VDDQ
Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
ODT0, ODT1
Input
Active
High
On-Die Termination control signals
BA0, BA1
(SSTL)
-
Selects which SDRAM bank is to be active.
A0 – A9
A10/AP
A11 – A13
(SSTL)
-
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address
(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,
AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write
cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be
precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
DQ0 – DQ63
(SSTL)
Active
High
Data and Check Bit Input/Output pins.
VDD, VSS
Supply
Power and ground for the DDR SDRAM input buffers and core logic
DQS0 – DQS7
–
(SSTL)
Negative
and
Positive
Edge
Data strobe for input and output data
DM0 – DM7
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.
SA0 – SA2
-
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
-
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pull-up.
SCL
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
VDDSPD
Supply
Serial EEPROM positive power supply.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30-1201100 | 22 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, CRIMP |
| M30-6000206R | 2 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| M30-6000306R | 3 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| M30-6000406R | 4 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| M30-6000506R | 5 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3 | 制造商:American Power Conversion Corp 功能描述:SURGE, 120KA PHASE MODULE 制造商:Panasonic Industrial Company 功能描述:SCREW |
| M-3 | 功能描述:TERM BARRIER 3CIRC DUAL ROW RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:M 標準包裝:10 系列:32500 端接塊類型:阻隔塊 電路數(shù):13 導線入口數(shù)目:13 間距:0.325"（8.255mm） 行數(shù):1 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘（不包括） 底部端子:焊接轉(zhuǎn)塔 阻擋層類型:三壁（三） 特點:法蘭 顏色:- 包裝:散裝 安裝類型:通孔 工作溫度:105°C 材料 - 絕緣體:聚丙烯（PP） 材料可燃性額定值:UL94 V-0 |
| M3 BRASS FULL WASHER | 制造商:Farnell / Duratool 功能描述:WASHER FULL BRASS M3 制造商:Farnell / Duratool 功能描述:WASHER, FULL, BRASS, M3 制造商:Farnell / Duratool 功能描述:WASHER, FULL, BRASS, M3; Fastener Material:Brass; Material:Brass; Thread Size - Metric:M3; Thread Type:Metric ;RoHS Compliant: NA 制造商:Farnell / Duratool 功能描述:WASHER, FULL, BRASS, M3; Fastener Material:Brass; Thread Type:Metric; Material:Brass; Thread Size - Metric:M3 ;RoHS Compliant: NA |
| M3 D1N985 A2 | 制造商:NUTS 功能描述: |
| M3- DNA2-S50- | 制造商:TR FASTENINGS 功能描述:DOME NUT S/S A2 M3 制造商:TR FASTENINGS 功能描述:DOME NUT, S/S, A2, M3 制造商:TR FASTENERS 功能描述:DOME NUT, S/S, A2, M3, Thread Size - Imperial:-, Thread Size - Metric:M3, Fasten 制造商:TR FASTENINGS 功能描述:DOME NUT, S/S, A2, M3, Thread Size - Imperial:-, Thread Size - Metric:M3, Fastener Material:Stainless Steel, Fastener Plating:(Not Available), SVHC:No SVHC (19-Dec-2012), Material:Stainless Steel, Thread Size:M3 , RoHS Compliant: Yes |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。