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參數(shù)資料
| 型號： | M2Y51264TU88A2G-37B |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 444K |
| 代理商： | M2Y51264TU88A2G-37B |
M2Y51264TU88A2G/ M2Y1G64TU8HA2G
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.0
7
6/2006
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect – Part 1 of 2 (512MB)
64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Byte
Description
667 -3C
533 -37B
667 -3C
533 -37B
Note
0
Number of Serial PD Bytes Written during Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type (FPM, EDO.SRDAM, DDR,
DDR2…)
DDR2
08
3
Number of Row Addresses on Assembly
14
0E
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Bank, Package and Height
1 rank, Height >30.5mm
A0
6
Data Width of This Assembly
64
40
7
Reserved
Undefined
00
8
Voltage Interface Level of this Assembly
SSTL_1.8V
05
9
DDR2 SDRAM Device Cycle Time at Maximum Support /CAS
Latency CL=5
3ns
3.75ns
30
3D
10
DDR2 SDRAM Device Access Time (tac) from Clock at CL=5
0.45ns
0.5ns
45
50
11
DIMM Configuration Type (non-parity, parity or ECC)
Non Parity/ECC
00
12
Refresh Rate/Type
7.89s/self
82
13
Primary DDRII SDRAM Width
x8
08
14
Error Checking DDRII SDRAM Device Width
N/A
00
15
Reserved
Undefined
00
16
DDR SDRAM Device Attributes: Burst Lengths Supported
4,8
0C
17
DDR SDRAM Device Attributes: Number of Banks on DDRII
SDRAM Device
4
04
18
DDR SDRAM Device Attributes: /CAS Latencies Supported
5,4,3
38
19
DIMM Mechanical Characteristics
<4.10mm
01
20
DIMM type information
Regular UDIMM(133.35mm)
02
21
DDRII SDRAM Modules Attributes
Normal DIMM
00
22
DDRII SDRAM Device Attributes: General
Support weak driver
03
01
23
Minimum Clock Cycle Time at CL=4
3.75ns
3D
24
Maximum Data Access Time (tAC) from Clock at CL=4
0.5ns
50
25
Minimum Clock Cycle Time at CL=3
5.0ns
50
26
Maximum Data Access Time (tAC) from Clock at CL=3
0.6ns
60
27
Minimum Row Precharge Time (tRP)
15ns
3C
28
Minimum Row Active to Row Active delay (tRRD)
7.5ns
1E
29
Minimum RAS to CAS delay (tRCD)
15.0ns
3C
30
Minimum Active to Precharge Time (tRAS)
45.0
2D
31
Module Bank Density
512MB
80
32
Address and Command Input Setup Time Before Clock (tIS)
0.2ns
0.25ns
20
25
33
Address and Command Input Hold Time After Clock (tIH)
0.275ns
0.375ns
27
37
34
Data Input Setup Time Before Clock (tDS)
0.10ns
10
35
Data Input Hold Time After Clock (tDH)
0.175ns
0.225ns
17
22
36
Write recovery time (tWR)
15.0ns
3C
37
Internal write to read command delay (tWTR)
7.5ns
1E
38
Internal Read to Precharge command delay(tRTP)
7.5ns
1E
39
Memory Analysis Probe Characteristics
Undefined
00
40
Extension of Byte 41 tRC and Byte 42 tRFC
The number below a decimal
point of tRC and tRFC are 0,
tRFC is less than 256ns
00
41
SDRAM Device Minimum Active to Active/Auto-Refresh Time
(tRC)
60.0ns
3C
42
SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh
Command Period (tRFC)
105ns
69
43
SDRAM Device Maximum Cycle Time (tCK max)
8.0ns
80
44
SDRAM Device Maximum skew between DQS and DQ signals
(tDQS)
0.24ns
0.30ns
18
1E
45
SDRAM Device Maximum Read Data Hold Skew Factor
(tQHS)
0.34ns
0.40ns
22
28
46
PLL Relock Time
N/A
00
47
Tcasemax
DT4R4W Delta
95 :
0.8 :
95 :
0.4 :
52
51
48
Thermal Resistance of DRAM Package from Top (Case) to
Ambient ( Psi T-A DRAM )
61 : /W
7A
49
DRAM Case Temperature Rise from Ambient due to
Activate-Precharge/Mode Bits (DT0/Mode Bits)
8.8 :
8.2 :
53
4B
50
DRAM Case Temperature Rise from Ambient due to
Precharge/Quiet Standby(DT2N/DT2Q)
5.8 :
4.6 :
3A
2E
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