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參數(shù)資料
| 型號： | M2V28D30ATP-75 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 128M Double Data Rate Synchronous DRAM |
| 中文描述： | 128M的雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 1216K |
| 代理商： | M2V28D30ATP-75 |
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13
MITSUBISHI ELECTRIC
Jun,'00
Preliminary
MITSUBISHI LSIs
DDR SDRAM (Rev.0.1)
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the DDR SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from
a MRS command, the DDR SDRAM is ready for new command.
/CS
/RAS
/CAS
/WE
A11-A0
/CLK
V
CLK
BA0
BA1
R: Reserved for Future Use
0
1
NO
YES
DLL Reset
0
1
Sequential
Interleaved
Burst Type
BT=0
R
2
4
8
R
R
R
R
BT=1
R
2
4
8
R
R
R
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BL
Burst
Length
/CAS Latency
R
R
2
R
R
R
2.5
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CL
Latency
Mode
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
DR
0
BT
LTMODE
BL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2V28D40ATP-10 | 128M Double Data Rate Synchronous DRAM |
| M2V28D40ATP-75 | 128M Double Data Rate Synchronous DRAM |
| M2S28D20ATP | 128M Double Data Rate Synchronous DRAM |
| M2S28D20ATP-10 | 128M Double Data Rate Synchronous DRAM |
| M2S28D20ATP-75 | 128M Double Data Rate Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V28D40ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28D40ATP-75 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM |
| M2V28S20ATP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S20ATP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S20ATP-6L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
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