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參數(shù)資料
| 型號： | M2V12D20TP-75L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 512M Double Data Rate Synchronous DRAM |
| 中文描述： | 512M雙數(shù)據(jù)速率同步DRAM |
| 文件頁數(shù)： | 13/38頁 |
| 文件大小： | 754K |
| 代理商： | M2V12D20TP-75L |
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MITSUBISHI
ELECTRIC
-13-
M2S12D20/ 30TP -75, -75L, -10, -10L
512M Double Data Rate Synchronous DRAM
Feb. '02
MITSUBISHI LSIs
DDR SDRAM (Rev.1.1)
MITSUBISHI ELECTRIC
POWER ON SEQUENCE
The following power on sequences are necessary to guarantee the proper operations of the
DDR SDRAM.
1. Apply VDD before or at the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable conditions for 200us after stable power and CLK are supplied, assert NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS to program proper functions
6. Issue MRS to configure the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable conditions for 200 cycle
After these sequence, the DDR SDRAM is in the idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be
programmed by configuring the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from
an MRS command, the DDR SDRAM is ready to accept the new
command.
/CS
/RAS
/CAS
/WE
A12-A0
/CLK
V
CLK
BA0
BA1
R: Reserved for Future Use
0
1
NO
YES
DLL Reset
0
1
Sequential
Interleaved
Burst Type
BT=0
R
2
4
8
R
R
R
R
BT=1
R
2
4
8
R
R
R
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BL
Burst
Length
/CAS Latency
R
R
2
R
R
R
2.5
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CL
Latency
Mode
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
DR
0
BT
LTMODE
BL
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