參數(shù)資料
型號: M25PE80-VMN6TP
廠商: 意法半導體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 59/61頁
文件大?。?/td> 326K
代理商: M25PE80-VMN6TP
M25PE80
Revision history
59/61
14
Revision history
Table 29.
Document revision history
Date
Version
Changes
24-Nov-2004
0.1
First Issue.
07-Dec-2004
0.2
4KB Software protection granularity extended to Sector 15.
10-May-2005
0.3
SO16W package removed, SO8W package added.
End timing line of t
SHQZ
modified in
Figure 28: Output timing
. Plating
Technology options modified in
Table 28: Ordering information scheme
.
Minor text changes.
Tables
2
and
3
and
Figure 6
for details on the software protection scheme.
25-Jul-2005
0.4
Lock Register programming sequence detailed in Section
Write to Lock
Register (WRLR)
.
Sections
An easy way to modify data
,
A fast way to modify data
,
Page
Write (PW)
and
Page Program (PP)
, updated to explain when using Page
Write and Page Program instructions.
Bulk Erase cycle time (t
BE
), Page Write cycle time (t
PW
) and Page
Program cycle time (t
PP
) updated in
Table 21: AC characteristics
.
24-Aug-2005
1.0
Version number updated for internet. No document changes.
25-Aug-2005
2.0
Document status updated to Preliminary Data.
22-Nov-2005
3.0
Page Program cycle time, t
PP
, and Page Write Cycle Time (n Bytes), t
PW
,
updated in
Table 21: AC characteristics
. I
CC3
modified in
Table 20: DC
characteristics
.
t
SLCH
, t
CHSL
, t
CHSH
, t
SHCH
and t
BE
modified in
Table 21: AC
characteristics
.
MLP package renamed. Under
Plating technology
, Blank option removed.
Note 3
to
Table 21
modified. Address modified in
Figure 6: Block diagram
.
Note added to
Figure 30
and
Figure 31
.
Document status promoted from Preliminary Data to full Datasheet status.
12-May-2006
4
Don’t care address bits modified in
Note 1
(below
Figure 12
),
Note 1
(below
Figure 13
),
Note 1
(below
Figure 15
),
Note 1
(below
Figure 16
),
Note 1
(below
Figure 18
) and
Note 1
(below
Figure 20
).
Small text changes.
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