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參數(shù)資料
| 型號： | M25PE20-VMP6G |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 59/60頁 |
| 文件大?。?/td> | 310K |
| 代理商： | M25PE20-VMP6G |
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M25PE20, M25PE10
Revision history
59/60
14
Revision history
Table 28.
Document revision history
Date
Version
Changes
07-Dec-2004
0.1
Document written
21-Dec-2004
0.2
Notes 1 and 2 removed from
Table 27: Ordering information scheme
.
S08N silhouette corrected
on page 1
.
6-Oct-2005
1.0
Added <Blue>Table 21., AC characteristics (33 MHz operation).
Document status promoted to full Datasheet.
An easy way to modify
data
,
A fast way to modify data
,
Page Write (PW)
and
Page Program
(PP)
sections updated to explain optimal use of Page Write and Page
Program instructions. Clock slew rate changed from 0.03 to 0.1 V/ns.
Updated <Blue>Table 27., Ordering information scheme. Added
Ecopack information.
10-Jul-2006
2
Document converted to the new ST template.
MLP package removed, SO8N package specifications updated (see
Section 12: Package mechanical
).
Figure 5: SPI modes supported
updated and
Note 2
added. Timing line
of t
SHQZ
moved in
Figure 29
.
25-Jan-2007
3
50 MHz frequency added. VFQFPN package added (see
Section 12:
Package mechanical
).
The sectors are further divided up into subsectors (see
Table 5:
M25PE20 memory organization
and
Table 6: M25PE10 memory
organization
).
Important note on page 6
added.
Figure 4: Bus master
and memory devices on the SPI bus
updated and explanatory paragraph
added.
VCC supply voltage
and
VSS ground
added.
Section 4.8:
Protection modes
modified.
Section 8: Reset
added, Reset timings table
split into
Table 23: Reset conditions
and
Table 24: Timings after a Reset
Low pulse
.
At Power-up the WIP bit is reset and the Lock Registers are reset (see
Section 7: Power-up and power-down
).
V
IO
max changed in
Table 15: Absolute maximum ratings
.
M25PE20 and M25PE10 products processed in T9HX process added to
datasheet:
– WP pin replaces TSL (T7X technology), see
Section 2.7: Write Protect
(W) or Top Sector Lock (TSL)
–
Read Lock Register (RDLR)
,
Write to Lock Register (WRLR)
,
Write
Status Register (WRSR)
,
SubSector Erase (SSE)
and
Bulk Erase
(BE)
instructions added for T9HX process
– subsector protection granularity removed in T9HX process, still exists
in T7X process
–
Table 5: M25PE20 memory organization
and
Table 6: M25PE10
memory organization
updated to show subsectors
– Status Register
BP1, BP0 bits
and
SRWD bit
added.
Small text changes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M25PE20-VMP6P | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE20-VMP6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE10-VMN6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE10-VMN6TP | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE20 | 4 Mbit Uniform Sector, Serial Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25PE20-VMP6P | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE20-VMP6TG | 功能描述:IC FLASH 2MBIT 75MHZ 8VFQFPN RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Forté™ 標準包裝:2,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 異步 存儲容量:256K (32K x 8) 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:28-TSSOP（0.465"，11.8mm 寬） 供應(yīng)商設(shè)備封裝:28-TSOP 包裝:帶卷 (TR) 其它名稱:71V256SA15PZGI8 |
| M25PE20-VMP6TP | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE20-VMS6G | 制造商:Micron Technology Inc 功能描述: |
| M25PE20-VMW6G | 制造商:Micron Technology Inc 功能描述:SERIAL NOR - Trays |
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