參數(shù)資料
型號(hào): M25PE20-VMP6G
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 43/60頁
文件大小: 310K
代理商: M25PE20-VMP6G
M25PE20, M25PE10
Instructions
43/60
6.17
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Figure 24
.
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, t
RDP
, the device is put in
Standby Power mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 24.
Release from Deep Power-down (RDP) instruction sequence
C
D
AI06807
S
2
1
3
4
5
6
7
0
t
RDP
Standby Power Mode
Deep Power-down Mode
Q
High Impedance
Instruction
相關(guān)PDF資料
PDF描述
M25PE20-VMP6P 4 Mbit Uniform Sector, Serial Flash Memory
M25PE20-VMP6TG 4 Mbit Uniform Sector, Serial Flash Memory
M25PE10-VMN6TG 4 Mbit Uniform Sector, Serial Flash Memory
M25PE10-VMN6TP 4 Mbit Uniform Sector, Serial Flash Memory
M25PE20 4 Mbit Uniform Sector, Serial Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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M25PE20-VMP6TP 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout
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