參數(shù)資料
型號(hào)： M24C32
廠商： 意法半導(dǎo)體
英文描述： 32K Serial IIC Bus EEPROM(32K串行IIC總線EEPROM)
中文描述： 32K的串行IIC總線的EEPROM（32K的串行總線EEPROM的國(guó)際進(jìn)口許可證）
文件頁(yè)數(shù)： 12/35頁(yè)
文件大小： 330K
代理商： M24C32
Device operation
M24128, M24C64, M24C32
12/35
4
Device operation
The device supports the I
2
C protocol. This is summarized in
Figure 5
. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24C32, M24C64 and M24128
devices are always slaves in all communications.
4.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
4.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
th
clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
4.4
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change
only
when Serial Clock
(SCL) is driven Low.
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