M16C/30P Group
5. Electrical Characteristics
Rev.1.22
REJ03B0088-0122
Mar 30, 2007
Page 47 of 53
V
CC1
=V
CC2
=3V
Switching Characteristics
(V
CC1
= V
CC2
= 3V, V
SS
= 0V, at T
opr
=
20 to 85
°
C /
40 to 85
°
C unless otherwise specified)
NOTES:
1.
Calculated according to the BCLK frequency as follows:
)
n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less.
2.
Calculated according to the BCLK frequency as follows:
)
3.
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t =
CR X ln (1
V
OL
/ V
CC1
)
by a circuit of the right figure.
For example, when V
OL
= 0.2V
CC1
, C = 30pF, R = 1k
Ω
, hold time
of output ”L” level is
t =
30pF X 1k
Ω
X In(1
0.2V
CC1
/ V
CC1
)
= 6.7ns.
Table 5.44
Memory Expansion and Microprocessor Modes (for 1 wait setting and external area
access)
Symbol
Parameter
Standard
Min.
Unit
Max.
30
t
d(BCLK-AD)
t
h(BCLK-AD)
t
h(RD-AD)
t
h(WR-AD)
t
d(BCLK-CS)
t
h(BCLK-CS)
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(BCLK-RD)
t
h(BCLK-RD)
t
d(BCLK-WR)
t
h(BCLK-WR)
t
d(BCLK-DB)
t
h(BCLK-DB)
t
d(DB-WR)
th(WR-DB)
d(BCLK-HLDA)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
(3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
(3)
HLDA Output Delay Time
See
Figure 5.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
(NOTE 2)
30
0
25
-4
30
0
30
0
40
4
(NOTE 1)
(NOTE 2)
40
0.5
–
-n
40 ns
[
]
–
f BCLK
10 ns
]
–
DBi
R
C