M16C/30P Group
5. Electrical Characteristics
Rev.1.22
REJ03B0088-0122
Mar 30, 2007
Page 24 of 53
NOTES:
1.
2.
3.
Referenced to V
CC1
= V
CC2 =
2.7 to 5.5V at T
opr
=
20 to 85
°
C /
40 to 85
°
C unless otherwise specified.
The Average Output Current is the mean value within 100ms.
The total I
OL(peak)
for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total I
OL(peak)
for ports P3, P4, P5,
P6, P7 and P8_0 to P8_4 must be 80mA max. The total I
OH(peak)
for ports P0, P1, and P2 must be
40mA max. The total
I
OH(peak)
for ports P3, P4 and P5 must be
40mA max. The total I
OH(peak)
for ports P6, P7, and P8_0 to P8_4 must be
40mA
max.
The total I
OH(peak)
for ports P8_6, P8_7 and P9 must be
40mA max. Set Average Output Current to 1/2 of
peak
.
Relationship between main clock oscillation frequency, and supply voltage.
4.
Table 5.2
Recommended Operating Conditions
(1)
Symbol
Parameter
Standard
Typ.
5.0
V
CC
0
0
Unit
Min.
2.7
Max.
5.5
V
CC
AV
CC
V
SS
AV
SS
V
IH
Supply Voltage (V
CC1
=V
CC2
)
Analog Supply Voltage
Supply Voltage
Analog Supply Voltage
HIGH Input
Voltage
V
V
V
V
V
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7
0.8V
CC
0.8V
CC
V
CC
V
CC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, XIN, RESET, CNVSS, BYTE
P7_0, P7_1
0.5V
CC
V
CC
V
0.8V
CC
V
CC
V
0.8V
CC
0
0
6.5
V
V
V
V
IL
LOW Input
Voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7
0.2V
CC
0.2V
CC
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
V
CC
=3.0V to 5.5V
0
0.16V
CC
V
0
0.2V
CC
V
I
OH(peak)
HIGH Peak
Output Current
10.0
mA
I
OH(avg)
HIGH Average
Output Current
5.0
mA
I
OL(peak)
LOW Peak
Output Current
10.0
mA
I
OL(avg)
LOW Average
Output Current
5.0
mA
f(XIN)
Main Clock Input
Oscillation
Frequency
(4)
Sub-Clock Oscillation Frequency
CPU Operation Clock
0
0
16
MHz
MHz
V
CC
=2.7V to 3.0V
20×V
CC1
44
f(XCIN)
f(BCLK)
32.768
50
16
kHz
MHz
0
Main clock input oscillation frequency
16.0
0.0
f
VCC1[V] (main clock: no division)
5.5
3.0
10.0
2.7
20 x V
CC1
-44MHz