參數(shù)資料
型號(hào)： M12L2561616A-7TG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 4M x 16 Bit x 4 Banks Synchronous DRAM
中文描述： 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, TSOP2-54
文件頁(yè)數(shù)： 2/44頁(yè)
文件大?。?/td> 908K
代理商： M12L2561616A-7TG
ES MT
M12L2561616A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
Publication Date
:
Aug. 2007
2/44
BLOCK DIAGRAM
CS
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
CS
Chip Select
CKE
Clock Enable
A0 ~ A12
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA12, column address : CA0~CA8
BA1, BA0
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS
low. (Enables row access & precharge.)
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Enables write operation and row precharge.
WE
Write Enable
Latches data in starting from CAS ,
WE
active.
L(U)DQM
Data Input / Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
V
DD
/ V
SS
Power Supply / Ground
Power and ground for the input buffers and the core logic.
V
DDQ
/ V
SSQ
Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C
No Connection
This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
C
Column
Address
Buffer
&
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Bank C
R
Bank A
Bank B
Sense Amplifier
Column Decoder
Data Control Circuit
L
I
B
Address
Clock
Generator
CLK
CKE
C
RAS
CAS
WE
相關(guān)PDF資料
PDF描述
M12L32162A 1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A-7BG 1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A-7TG 1M x 16Bit x 2Banks Synchronous DRAM
M12L64164A-5BG 1M x 16 Bit x 4 Banks Synchronous DRAM
M12L64164A-6BG 1M x 16 Bit x 4 Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12L2561616A-7TG2K 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:JEDEC standard 3.3V power supply
M12L2561616A-7TIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Synchronous DRAM
M12L32162A 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A_0712 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A_09 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM
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