參數(shù)資料
型號: M12L2561616A-7TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 4M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 15/44頁
文件大?。?/td> 908K
代理商: M12L2561616A-7TG
ES MT
Self refresh entry command
(CS ,RAS ,CAS , CKE = Low ,
WE
= High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the M12L2561616A exits the self refresh
mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
(CS ,
WE
= Low,RAS ,CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
No operation
(CS = Low,RAS ,CAS ,
WE
= High)
This command is not an execution command. No operations begin or terminate
by this command.
M12L2561616A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
Publication Date
:
Aug. 2007
15/44
CLK
CKE
CS
RAS
WE
BA0, BA1
(Bank select)
A10
Add
CAS
CLK
CKE
CS
RAS
WE
BA0, BA1
(Bank select)
A10
Add
CAS
H
Fig. 7 Self refresh entry
command
Fig. 8 Burst stop command
CLK
CKE
CS
RAS
WE
BA0, BA1
(Bank select)
A10
Add
CAS
H
Fig. 9 No operation
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